| Patent Number |
Title Of Patent |
Date Issued |
| 6370623 |
Multiport register file to accommodate data of differing lengths |
April 9, 2002 |
| A multiport register file includes a first file unit having registers of a first width and a second file unite having registers of a second width. The second width being less than the first width. The first file unit accommodates data destined to be operands for functional units of a VLI |
| 6141675 |
Method and apparatus for custom operations |
October 31, 2000 |
| Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e. |
| 6122722 |
VLIW processor with less instruction issue slots than functional units |
September 19, 2000 |
| Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register. |
| 5978910 |
Performing pending interrupts or exceptions when interruptible jumps are detected |
November 2, 1999 |
| A circuit for processing a jump operation also enables handling pending interrupts or exceptions. The jump operation has an operand specifying a destination address. If an interrupt or exception is pending, a destination program counter is set to the contents of the operand. Then the |
| 5963744 |
Method and apparatus for custom operations of a processor |
October 5, 1999 |
| Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e. |
| 5832202 |
Exception recovery in a data processing system |
November 3, 1998 |
| A processing device performs operations in response to program instructions. In particular, values are written to a data memory of the system, which alters a defined visible state of the system. In the event of an exception (e.g. a pagefault or TLB miss in a virtual memory system), c |
| 5815701 |
Computer method and apparatus which maintains context switching speed with a large number of reg |
September 29, 1998 |
| Registers are divided into a global pool and a local pool. Code to be used in the processor must allocate registers from the global pool for values that live across decision trees and from the local pool for local values. The processor only accepts interrupts and exceptions during succes |
