| Patent Number |
Title Of Patent |
Date Issued |
| 5541132 |
Insulated gate semiconductor device and method of manufacture |
July 30, 1996 |
| An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein |
| 5408130 |
Interconnection structure for conductive layers |
April 18, 1995 |
| An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of condu |
| 5358890 |
Process for fabricating isolation regions in a semiconductor device |
October 25, 1994 |
| A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be con |
| 5324973 |
Semiconductor SRAM with trench transistors |
June 28, 1994 |
| A semiconductor memory cell (10) includes vertically disposed MOS pass transistors (32, 34) and MOS inverters (12, 14) contained in trench structures in a semiconductor substrate (11). An MOS inverter (12) has a toroidal shared-gate electrode (48) overlying the wall surface of a first |
| 5285093 |
Semiconductor memory cell having a trench structure |
February 8, 1994 |
| In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate ( |
| 5262352 |
Method for forming an interconnection structure for conductive layers |
November 16, 1993 |
| An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of condu |
| 5244824 |
Trench capacitor and transistor structure and method for making the same |
September 14, 1993 |
| A trench capacitor and transistor structure is formed in a semiconductor device. In one form, a transistor is fabricated within a cylindrical trench capacitor. The capacitor is formed within two displaced parallel planes in a substrate material, and has two electrodes which are separated |
| 5229310 |
Method for making a self-aligned vertical thin-film transistor in a semiconductor device |
July 20, 1993 |
| A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current elec |
| 5198683 |
Integrated circuit memory device and structural layout thereof |
March 30, 1993 |
| A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 o |
| 5082794 |
Method of fabricating MOS transistors using selective polysilicon deposition |
January 21, 1992 |
| In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process |
| 5061646 |
Method for forming a self-aligned bipolar transistor |
October 29, 1991 |
| A structure and process for fabricating a fully self-aligned high-performance bipolar semiconductor device is disclosed. In accordance with one embodiment of the invention, a substrate is provided having a first surface. A heavily doped buried layer is formed in the substrate extendi |
| 5006911 |
Transistor device with high density contacts |
April 9, 1991 |
| A transistor device has a gate centered in an active region in which the gate does not extend beyond the active region. The active region has stem portion for the gate and a branch portion extending from each side of the stem portion for the formation of contacts. Raised polysilicon cont |
| 4984042 |
MOS transistors using selective polysilicon deposition |
January 8, 1991 |
| In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process |
| 4948745 |
Process for elevated source/drain field effect structure |
August 14, 1990 |
| A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin |
| 4942137 |
Self-aligned trench with selective trench fill |
July 17, 1990 |
| A method for fabricating a self-aligned trench structure in a semiconductor device is disclosed. In accordance with one method for fabricating the trench structure, an oxidation resistant material having an opening is used as a masking layer. The edge of the opening in the masking layer |
