| Patent Number |
Title Of Patent |
Date Issued |
| RE32515 |
Apparatus for increasing the speed of a circuit having a string of IGFETS |
October 6, 1987 |
| In an IGFET circuit having a long string of more than two transistors connected in series between an output terminal and a power supply terminal where the load capacitance across the output terminal is on the same order of magnitude as the parasitic capacitances at the junctures of the |
| 6496056 |
Process-tolerant integrated circuit design |
December 17, 2002 |
| An operating parameter of an integrated circuit is made substantially insensitive to process variations by configuring the circuit such that an environmental parameter, e.g., supply voltage to a portion of the circuit, is made a function of one or more process parameters, e.g., conductio |
| 6366074 |
Unidirectionality in electronic circuits through feedback |
April 2, 2002 |
| A method for creating signal unidirectionality in electronic circuits is disclosed. This invention describes a method for achieving unidirectionality in an electronic circuit with an input side having a signal source and an output side with a load comprising detecting the current pas |
| 5959480 |
Digital signal transition edge alignment using interacting inverter chains |
September 28, 1999 |
| Apparatus and method for aligning signal transition edges in high-speed complementary metal-oxide-semiconductor (CMOS) integrated circuits and other electronic circuits, systems and devices. A transition edge alignment circuit in accordance with the invention includes first and secon |
| 5793942 |
Memory chip architecture and packaging method for increased production yield |
August 11, 1998 |
| A memory device and method of packaging to increase the production yield of large scale digital memory chips. The architecture provides the ability to house a plurality of partially defective memory chips into a single casing to provide the same memory as a non-defective chip, thus elimi |
| 5786827 |
Semiconductor optical storage device and uses thereof |
July 28, 1998 |
| A semiconductor memory device contains graphic information which is viewable both by direct, visual observation of the memory and electrically, e.g., via a TV screen. The device contains a semiconductor chip having a surface and an array of electrically addressable memory cells there |
| 5598365 |
High-density read-only memory |
January 28, 1997 |
| A system and method for the storage of digital information wherein data that would normally be represented by multiple bits of information is effectively stored at single memory site within a ROM. This is accomplished by employing a multiple bit-line memory architecture, in conjuncti |
| 5578952 |
Fixed-interval timing circuit and method |
November 26, 1996 |
| A system and method for generating a signal having a reliable, fixed duration and/or delay as a function of relative, not absolute, device characteristics. That is to say, the time period of the generated signal is determined as a ratio of one device's operating characteristics to an |
| 5528534 |
High-density read-only memory employing multiple bit-line interconnection |
June 18, 1996 |
| A system and method for the storage of digital information wherein data that would normally be represented by multiple bits of information is effectively stored at single memory site within a ROM. This is accomplished by employing a multiple bit-line memory architecture, in conjuncti |
| 5499208 |
Integrated circuit memory device |
March 12, 1996 |
| The present invention comprises a novel memory circuit wherein a plurality of memory cells have passive impedance values representative of the information stored therein. In the circuit, a signal source having a plurality of outputs is operable to provide a sequence of read signals, |
| 5418178 |
High-density read-only memory fabrication |
May 23, 1995 |
| A method for fabricating read-only memory ("ROM") devices utilizing junction field-effect transistors ("JFETs") having a conductive channel orthogonally oriented with respect to the surface of the semiconductor material composing the JFET. A fixed-position ion beam is employed to cre |
| 5117130 |
Integrated circuits which compensate for local conditions |
May 26, 1992 |
| Apparatus for compensating for the effect of a local condition on an active element in a portion of an integrated circuit. The apparatus includes a detecting element in the portion of the integrated circuit which is subject to the local condition and produces a response to the local |
| 4902912 |
Apparatus including resonant-tunneling device having multiple-peak current-voltage characteristi |
February 20, 1990 |
| A semiconductor integrated resonant-tunneling device having multiple negative-resistance regions, and having essentially equal current peaks in such regions, is useful as a highly compact element, e.g., in apparatus designed for ternary logic operations, frequency multiplication, wavefor |
| 4849751 |
CMOS Integrated circuit digital crossbar switching arrangement |
July 18, 1989 |
| A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, |
| 4782253 |
High speed MOS circuits |
November 1, 1988 |
| Integrated circuit chips with two (or more) multi-element logic paths--suffering from signal skew operation because of semiconductor processing variations--can be made to exhibit substantially reduced skew by designing the elements such that the sum of the pull-up delays in one logic |
| 4710650 |
Dual domino CMOS logic circuit, including complementary vectorization and integration |
December 1, 1987 |
| At each stage of a domino CMOS logic circuit, the output signal S and its inversion S are separately generated in mutually complementary first and second logic networks. These outputs S and S are then used as inputs for succeeding domino logic stages. In this way, both S and S are guaran |
| 4692637 |
CMOS logic circuit with single clock pulse |
September 8, 1987 |
| A dynamic, multistage CMOS logic circuit is driven with a single source of clock pulses. The clock pulses operate odd-numbered stages. A static delay circuit provides clock pulses to even-numbered stages. The dynamic and static circuits are designed according to a discipline that guarant |
| 4670670 |
Circuit arrangement for controlling threshold voltages in CMOS circuits |
June 2, 1987 |
| The threshold voltage of a CMOS circuit is stabilized by a feedback loop which responds to variations in threshold voltage of a reference FET to provide a backbias voltage to readjust the threshold voltage of a second FET. The circuit is particularly useful to overcome threshold variatio |
| 4668880 |
Chain logic scheme for programmed logic array |
May 26, 1987 |
| Additional data processing capability can be added to a programmed logic array (PLA), having an AND plane and an OR plane connected serially between an input register and an output register, by inserting a multistage domino CMOS logic network between the OR plane and the output regis |
| 4649296 |
Synthetic CMOS static logic gates |
March 10, 1987 |
| A multi-input CMOS integrated circuit gate is made with fewer PFETs connected between the source voltage and the output node than there are inputs. In many cases only a single PFET is employed. The inputs are applied through a logic network connected to the gate of the remaining PFET |
| 4585958 |
IC chip with noise suppression circuit |
April 29, 1986 |
| A microprocessor chip is adapted to maintain its databus at a reference voltage level during idle times between outputs. The arrangement enables like pull-up and pull-down delays as well as low noise levels to be achieved in the output circuits. |
| 4572972 |
CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down |
February 25, 1986 |
| An integrated circuit chip with a preferred ground structure and including only pull-down transistors (on-chip) is operated by means of an off-chip pull-up transistor arrangement for precharging the data bus to logic high. The arrangement exhibits relatively low noise characteristics all |
| 4516123 |
Integrated circuit including logic array with distributed ground connections |
May 7, 1985 |
| Logic arrays which apply outputs to logic circuitry are made to exhibit improved noise characteristics which, in turn, improve performance of the logic circuitry. The improvement is achieved by providing a distributed ground throughout the logic array to provide local closed loop paths f |
| 4514749 |
VLSI Chip with ground shielding |
April 30, 1985 |
| In VLSI chips, clock pulse skew is increasingly forbidding as one micron technology and operation at 25 megahertz is approached. Skew is avoided by encompassing the clock distribution line in such chips with ground lines to shield the distribution line from capacitive coupling to adjacen |
| 4514647 |
Chipset synchronization arrangement |
April 30, 1985 |
| Each chip of a microprocessor chipset is synchronized by an associated controller which adjusts a control signal for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp which compares the outp |
| 4488066 |
Databus coupling arrangement using transistors of complementary conductivity type |
December 11, 1984 |
| To improve the speed of transfer of information to the databus in data processing apparatus, the bus is periodically precharged and the coupling to the databus is by way of a special clocked CMOS buffer circuit. |
| 4479216 |
Skew-free clock circuit for integrated circuit chip |
October 23, 1984 |
| An op-amp feedback arrangement is used to provide non-skewed clock pulses from a source of skewed clock pulses. Any skew in the clock-in pulses results in a change in the average voltage of a clock-out pulse at the output of the arrangement. The average voltage of the clock-out pulse is |
| 4443882 |
Single terminal negative capacitance generator for response time enhancement |
April 17, 1984 |
| The combination of an amplifier with a capacitor connected between an input and output terminal is coupled to a data bus to effectively reduce the effective capacitance on the bus and thus enhance the response time of information sent through the data bus. |
| 4430583 |
Apparatus for increasing the speed of a circuit having a string of IGFETs |
February 7, 1984 |
| In an IGFET circuit having a long string of more than two transistors connected in series between an output terminal and a power supply terminal where the load capacitance across the output terminal is on the same order of magnitude as the parasitic capacitances at the junctures of the |
| 4422141 |
Microprocessor architecture for improved chip testability |
December 20, 1983 |
| An improved architecture for a single chip microprocessor CPU includes provision for directly observing at its terminals the control signals from its instruction decoder to facilitate functional testing of the chip. The CPU, upon receiving a command signal transfers the signals on the co |
| 4403287 |
Microprocessor architecture having internal access means |
September 6, 1983 |
| A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an I |
| 4320409 |
Complementary field-effect transistor integrated circuit device |
March 16, 1982 |
| A CMOS integrated circuit structure having an improved guardband configuration for the prevention of parasitic SCR latchup. Included with each guardband is a pair of field reducing surface regions of the opposite conductivity type to that of the guardband and situated one on each side |
| 4176344 |
Integrated circuit binary weighted digital-to-analog converter |
November 27, 1979 |
| An integrated circuit digital-to-analog converter circuit of the binary weighted current summing type in which the emitter potentials of the transistor current sources are maintained substantially equal by controlling the voltage differential between the base electrodes of the curren |
| 3965453 |
Piezoresistor effects in semiconductor resistors |
June 22, 1976 |
| In semiconductor integrated circuits, piezoresistance is recognized as a factor affecting production yield and circuit performance. Current flow in a circuit resistor is aligned with one of the <100> family of equivalent directions. When current is flowing along such a direction th |
