| Patent Number |
Title Of Patent |
Date Issued |
| 7608509 |
Method of manufacturing a flash memory device having compensation members formed on edge portion |
October 27, 2009 |
| In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is form |
| 7557388 |
MOSFET formed on a strained silicon layer |
July 7, 2009 |
| A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is |
| 7553742 |
Method(s) of forming a thin layer |
June 30, 2009 |
| A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insul |
| 7537980 |
Method of manufacturing a stacked semiconductor device |
May 26, 2009 |
| In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially fillin |
| 7521331 |
High dielectric film and related method of manufacture |
April 21, 2009 |
| A method of forming a high dielectric film for a semiconductor device comprises supplying a first source gas to a reaction chamber during a first time interval, supplying a first reactant gas to the reaction chamber during a second time interval after the first time interval, supplyi |
| 7501674 |
Semiconductor device having fin transistor and planar transistor and associated methods of manuf |
March 10, 2009 |
| Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transist |
| 7494859 |
Semiconductor device having metal gate patterns and related method of manufacture |
February 24, 2009 |
| A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises |
| 7442596 |
Methods of manufacturing fin type field effect transistors |
October 28, 2008 |
| A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the su |
| 7422965 |
Methods of fabricating p-type transistors including germanium channel regions |
September 9, 2008 |
| A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-c |
| 7396761 |
Semiconductor device and method of manufacturing the same |
July 8, 2008 |
| In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is |
| 7390719 |
Method of manufacturing a semiconductor device having a dual gate structure |
June 24, 2008 |
| A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first |
| 7364990 |
Epitaxial crystal growth process in the manufacturing of a semiconductor device |
April 29, 2008 |
| First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection stru |
| 7351622 |
Methods of forming semiconductor device |
April 1, 2008 |
| A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second sourc |
| 7326608 |
Fin field effect transistor and method of manufacturing the same |
February 5, 2008 |
| In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon |
| 7315063 |
CMOS transistor and method of manufacturing the same |
January 1, 2008 |
| A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conducti |
