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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Shimizu; Kazuhiro
Address:
Tokyo, JP
No. of patents:
21
Patents:












Patent Number Title Of Patent Date Issued
8044487 Semiconductor device and method of manufacturing the same October 25, 2011
A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS
7977787 Semiconductor device July 12, 2011
A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern
7777279 Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of August 17, 2010
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p.sup.+-type impurity region is formed between a
7763950 Semiconductor device with multi-trench separation region July 27, 2010
A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using multiple partition wal
7741695 Semiconductor device June 22, 2010
Extending from an upper surface of an n.sup.- semiconductor layer on a p.sup.- semiconductor substrate to the interface between the n.sup.- semiconductor layer and the p.sup.- semiconductor substrate, a p.sup.+ impurity region is provided. The p.sup.+ impurity region defines a high-p
7582946 Semiconductor device with multi-trench separation region and method for producing the same September 1, 2009
A semiconductor device is configured that a high-withstand voltage semiconductor device (101) and logic circuits (201 and 301) are integrated on a single chip and that a high-withstand voltage high-potential island (402) including the high-potential-side logic circuit (301) is separa
7545005 Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of June 9, 2009
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p.sup.+-type impurity region is formed between a
7521982 Drive circuit for driving power device April 21, 2009
A drive circuit for driving a power device has a level shift circuit which level-shifts an ON signal and an OFF signal for controlling the power device in ON and OFF states, respectively, and which outputs the level-shifted ON and OFF signals, a mask circuit which stops transmission
7481885 Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semi January 27, 2009
A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which ejects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern
7439122 Method of manufacturing semiconductor device having improved RESURF Trench isolation and method October 21, 2008
A p impurity region (3) defines a RESURF isolation region in an n.sup.- semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n.sup.- semiconductor layer (2) in the RESURF isolation region. An nMOS tr
7408228 Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of August 5, 2008
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p.sup.+-type impurity region (33) is formed
7327007 Semiconductor device with high breakdown voltage February 5, 2008
A technique is provided which allows easy achievement of a semiconductor device with desired breakdown voltage. In a high-potential island region defined by a p impurity region, an n.sup.+ impurity region is formed in an n.sup.- semiconductor layer, and first field plates and second fiel
7294901 Semiconductor device with improved resurf features including trench isolation structure November 13, 2007
A p impurity region (3) defines a RESURF isolation region in an n.sup.- semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n.sup.- semiconductor layer (2) in the RESURF isolation region. An nMOS tr
7190034 Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of March 13, 2007
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p.sup.+-type impurity region (33) is formed
7049850 Semiconductor device with a voltage detecting device to prevent shoot-through phenomenon in firs May 23, 2006
An HNMOS transistor (4) has its drain electrode connected to the gate electrode of an NMOS transistor (21), and a logic circuit voltage (VCC) is applied to the drain electrode of the NMOS transistor (21) through a resistor (32). A ground potential is applied to the source electrode of
6844613 Semiconductor device January 18, 2005
A floating electrode (201) and an electrode (202) are coupled together by an electrostatic capacitance (C1), the floating electrode (201) and an electrode (203) are coupled together by an electrostatic capacitance (C2), and an electrode (200) and the floating electrode (201) are coupled
6838745 Semiconductor device having a separation structure for high withstand voltage January 4, 2005
An n-type well is formed in a p.sup.- -type semiconductor substrate and a p.sup.- -type epitaxial layer is formed on; the n-type well. An n.sup.- -type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF operation. A p-type island is formed in the n.s
6507085 Semiconductor device comprising diode January 14, 2003
A semiconductor device is provided which minimizes a reduction in the breakdown voltage caused by a metal electrode to which a high voltage is applied. An n.sup.- semiconductor layer (3) is formed on a p.sup.- semiconductor substrate (1). A p.sup.+ impurity region (4) is formed withi
6218712 Semiconductor device and method of manufacturing same April 17, 2001
A semiconductor device includes a pair of second semiconductor regions (5) selectively formed in predetermined spaced apart relation in a first semiconductor region (3), and a silicide film (8) formed in an upper main surface of the first semiconductor region (3) between the pair of seco
5894156 Semiconductor device having a high breakdown voltage isolation region April 13, 1999
A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is
5703515 Timing generator for testing IC December 30, 1997
A timing generator which receives a rate signal and generates an output signal based on the rate signal, and comprises at least two delay lines for causing delays in the rate signal, a formatter for receiving signals from the delay lines and for determining the rise and fall of an output










 
 
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