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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Shimamune; Yosuke
Address:
Kawasaki, JP
No. of patents:
26
Patents:












Patent Number Title Of Patent Date Issued
8586438 Semiconductor device and manufacturing method thereof November 19, 2013
Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.
8293622 Semiconductor device fabrication method, semiconductor device, and semiconductor layer formation October 23, 2012
A semiconductor device fabrication method and a semiconductor layer formation method for making a semiconductor layer having excellent morphology selectively epitaxial-grow over a semiconductor, and a semiconductor device. When a recessed source/drain pMOSFET is fabricated, a gate el
8288757 Semiconductor device and manufacturing method thereof October 16, 2012
A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A
8278177 Semiconductor device and method of manufacturing the same October 2, 2012
A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first
8232191 Semiconductor device manufacturing method July 31, 2012
A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over th
8207042 Semiconductor device and method of manufacturing the same June 26, 2012
A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first
8164085 Semiconductor device and production method thereof April 24, 2012
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
8158498 P-channel MOS transistor and fabrication process thereof April 17, 2012
A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of
7985641 Semiconductor device with strained transistors and its manufacture July 26, 2011
A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor
7968414 Semiconductor device and production method thereof June 28, 2011
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7875521 Semiconductor device and production method thereof January 25, 2011
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7816766 Semiconductor device with compressive and tensile stresses October 19, 2010
A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate e
7791064 Semiconductor device and fabrication method thereof September 7, 2010
A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation film
7683362 Semiconductor device and production method thereof March 23, 2010
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7679147 Semiconductor device fabricated by selective epitaxial growth method March 16, 2010
A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed o
7667227 Semiconductor device and fabrication method thereof February 23, 2010
A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation film
7626215 Semiconductor device and method of manufacturing the same December 1, 2009
A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first
7579617 Semiconductor device and production method thereof August 25, 2009
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7518188 P-channel MOS transistor and fabrication process thereof April 14, 2009
A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of
7476941 Semiconductor integrated circuit device and fabrication process thereof January 13, 2009
A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective
7446394 Semiconductor device fabricated by selective epitaxial growth method November 4, 2008
A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed o
7390707 Semiconductor device fabrication method June 24, 2008
The semiconductor device fabrication method comprising the step of forming a gate electrode on a semiconductor substrate; the step of forming a source/drain diffused layer in the semiconductor substrate on both sides of the gate electrode; the step of burying a silicon germanium layer in
7378305 Semiconductor integrated circuit and fabrication process thereof May 27, 2008
A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate e
7262465 P-channel MOS transistor and fabrication process thereof August 28, 2007
A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si laye
7202120 Semiconductor integrated circuit device and fabrication process thereof April 10, 2007
A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective
7033868 Semiconductor device and method of manufacturing same April 25, 2006
A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a










 
 
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