| Patent Number |
Title Of Patent |
Date Issued |
| 6242307 |
Method of fabricating flash memory |
June 5, 2001 |
| A method for fabricating a flash memory. A bar-shaped first oxide layer and a bar-shaped first conductive layer are formed on a substrate. A mask layer is formed to cover one side of the first conductive layer from portions of the top surface of the first conductive layer to portions of |
| 6180459 |
Method for fabricating a flash memory with shallow trench isolation |
January 30, 2001 |
| A method for fabricating a flash memory is provided. The method contains sequentially forming a tunnel oxide layer, a first polysilicon layer, and a silicon nitride layer on a semiconductor substrate. A shallow trench isolation (STI) structure is formed in the substrate to define an acti |
| 6157057 |
Flash memory cell |
December 5, 2000 |
| A flash memory cell. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. |
| 6066572 |
Method of removing carbon contamination on semiconductor substrate |
May 23, 2000 |
| A method of removing carbon contamination. On a semiconductor substrate having carbon contamination thereon, a sacrificial oxide layer is formed. During the formation of the sacrificial oxide layer, an agent is introduced to help and improve the growth of the sacrificial oxide layer, |
| 6051469 |
Method of fabricating bit line |
April 18, 2000 |
| A method of fabricating a bit line on a semiconductor substrate is provided. First, an oxide layer is formed and patterned on the substrate. An epitaxial layer is formed on the exposed substrate after patterning the oxide layer. A first spacer and a second spacer are sequentially formed |
| 6008522 |
Structure of buried bit line |
December 28, 1999 |
| The structure of a buried bit line. A substrate is provided and a trench is, formed within the substrate. Next, a trench insulating layer is located on a portion of the trench surface to expose a top corner of the trench. Then, a first conductive layer is fills the trench and forms a |
| 5994185 |
Method of fabricating flash memory cell |
November 30, 1999 |
| A method of fabricating a flash memory. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the |
| 5915171 |
Process of fabricating an antifuse structure |
June 22, 1999 |
| An antifuse structure for semiconductor programmable logic devices and the process of fabrication are described. The antifuse structure has its bottom electrically conductive layer featuring sharp corners formed by consumption of the polysilicon material into the sidewall in a thermal |
| 5907172 |
Split-gate flash memory cell structure |
May 25, 1999 |
| A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating |
| 5882972 |
Method of fabricating a buried bit line |
March 16, 1999 |
| A method of fabricating a buried bit line. An insulating layer is formed on a substrate, a trench is formed within the substrate by patterning the insulating layer and the substrate and then a liner oxide is formed on the trench surface. Then, a first conductive layer is formed on the in |
| 5872036 |
Method of manufacturing a split-gate flash memory cell |
February 16, 1999 |
| A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating |
| 5856224 |
Method of fabricating split-gate flash memory |
January 5, 1999 |
| A method of fabricating split-gate slash memory can define source and drain regions by using a self-alignment process. Thus, the uniformity of the split-gate flash memory performance is better controlled. This method comprises a floating gate oxide layer, a first polysilicon layer and a |
| 5646059 |
Process for fabricating non-volatile memory cells having improved voltage coupling ratio by util |
July 8, 1997 |
| A process for fabricating non-volatile memory cells having improved voltage coupling ratio by utilizing liquid phase deposition. Polysilicon spacers resulting from the liquid phase deposition increase the surface area of the dielectric layer between floating gate and control gate layers. |
| 5422292 |
Process for fabricating split gate flash EEPROM memory |
June 6, 1995 |
| A new process for fabricating split-gate flash EEPROM memory cell on a semiconductor substrate is described. Source/drain regions are formed apart in the semiconductor substrate to define a channel there between. A tunnel oxide layer, a first conducting layer, and an dielectric layer are |
