| Patent Number |
Title Of Patent |
Date Issued |
| 6911604 |
Bonding pads of printed circuit board capable of holding solder balls securely |
June 28, 2005 |
| A printed circuit board, which comprises a substrate, a conductive pattern disposed on a surface of said substrate and a solder mask coated on the surface of said substrate and covered over the conductive pattern. The conductive pattern has a bonding pad. The solder mask has an opening |
| 6857865 |
Mold structure for package fabrication |
February 22, 2005 |
| A mold structure for package fabrication is proposed, and includes a top mold, a fixture and a bottom mold. The top mold is formed with at least an upwardly recessed portion; the fixture is formed with a plurality of downwardly recessed portions; and the bottom mold has a recessed cavity |
| 6849932 |
Double-sided thermally enhanced IC chip package |
February 1, 2005 |
| The present invention is to provide a double-sided thermally enhanced IC chip package which includes a chip being received in an opening of a substrate and electrically connected to a conductive circuit pattern on a top surface of the substrate through bonding wires. A thermally and |
| 6713856 |
Stacked chip package with enhanced thermal conductivity |
March 30, 2004 |
| A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and |
| 6709894 |
Semiconductor package and method for fabricating the same |
March 23, 2004 |
| A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the |
| 6683385 |
Low profile stack semiconductor package |
January 27, 2004 |
| A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to |
| 6614660 |
Thermally enhanced IC chip package |
September 2, 2003 |
| A thermally enhanced IC chip package has a dielectric substrate member with conductive circuit patterns on top and bottom surfaces thereof and an opening therethrough. An IC chip having active and inactive sides is received in the opening. The active side of the chip and the top surface |
| 6555919 |
Low profile stack semiconductor package |
April 29, 2003 |
| A low profile stack semiconductor package is proposed, wherein at least two chips having centrally-situated bond pads are stacked on a substrate that is formed with a through opening. A first chip is mounted on the substrate, with bond pads thereof being exposed to the opening. A second |
