| Patent Number |
Title Of Patent |
Date Issued |
| 7516259 |
Combined engine for video and graphics processing |
April 7, 2009 |
| The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration |
| 7432988 |
Address generation for video processing |
October 7, 2008 |
| A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a m |
| 7411628 |
Method and system for scaling, filtering, scan conversion, panoramic scaling, YC adjustment, and |
August 12, 2008 |
| Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by re |
| 7380036 |
Combined engine for video and graphics processing |
May 27, 2008 |
| The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration |
| 7376288 |
Edge adaptive demosaic system and method |
May 20, 2008 |
| A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a |
| 7366238 |
Noise filter for video processing |
April 29, 2008 |
| A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blo |
| 7333678 |
Edge adaptive demosaic system and method |
February 19, 2008 |
| A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a |
| 7310785 |
Video processing architecture definition by function graph methodology |
December 18, 2007 |
| A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique |
| 7259796 |
System and method for rapidly scaling and filtering video data |
August 21, 2007 |
| This invention relates generally to hardware for scaling and filtering video data and more specifically to algorithms and techniques for accelerating scaling and filtering operations on digital video data. The hardware is designed so that scaling and filtering operations are combined |
| 7219173 |
System for video processing control and scheduling wherein commands are unaffected by signal int |
May 15, 2007 |
| A method, apparatus, computer medium, and other embodiments for synchronizing control of one or more devices at predetermined times are described. A host scheduler loads a to-do list of predetermined events and corresponding time-tags into memory and broadcasts scheduled events to th |
| 7142251 |
Video input processor in multi-format video compression system |
November 28, 2006 |
| A video input processor is provided to process different input video format, including RGB, RGB Bayer, YUV 4:2:2 interlaced and progressive video data. The video input processor also uses an advanced algorithm to efficiently convert video data in RGB color space to YUV color space. The |
| 7085320 |
Multiple format video compression |
August 1, 2006 |
| A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware p |
| 7035332 |
DCT/IDCT with minimum multiplication |
April 25, 2006 |
| A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes two sets of lookup t |
| 6996702 |
Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including |
February 7, 2006 |
| A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system |
| 6981073 |
Multiple channel data bus control for video processing |
December 27, 2005 |
| A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of a |
| 6970509 |
Cell array and method of multiresolution motion estimation and compensation |
November 29, 2005 |
| A method, apparatus, computer medium, and other embodiments for motion estimation and compensation processing of video and image signals are described. Within a sequence of frames, block-based differences are taken between frames to exploit redundancies between pictures by taking a m |
