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Seno; Katsunori
Kanagawa, JP
No. of patents:

Patent Number Title Of Patent Date Issued
6924679 Power supply control device, semiconductor device and method of driving semiconductor device August 2, 2005
A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and a semiconductor circuit and a method for driving the same, having a semiconductor circuit 11, an input signal generation c
6414527 Semiconductor device replica circuit for monitoring critical path and construction method of the July 2, 2002
A semiconductor device provided with a replica circuit functioning as an equivalent circuit to that of a path configuration selected as a critical path in the semiconductor circuit and an adjustable delay device for example between an output side of the replica circuit and a phase co
6313622 Power source voltage controller November 6, 2001
A power source voltage controller which can set the optimal margin for a replica circuit and shorten the time for the power source voltage to converge to the optimal value, having a replica circuit for monitoring a delay time of a critical path by propagating a reference signal having a
6295242 SRAM with current-mode test read data path September 25, 2001
A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the
6222410 Semiconductor circuit April 24, 2001
A semiconductor circuit capable of keeping the leakage current to a minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to a maximum, wherein delay paths to which low threshold voltage gate elements are applied are restricted to delay
5757689 Semiconductor memory activated by plurality of word lines on same row May 26, 1998
A semiconductor memory device including a plurality of memory cells arranged in a matrix; a plurality of bit lines; and a plurality of word lines controlled by column addresses for the same row addresses of the memory cells, wherein memory cells belonging to the same row are operativ
5528187 Clock synchronizing circuit June 18, 1996
Clock signals of the same phase are formed even when signal delays occur in clock signals transmitted on a clock line. In a clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, the clock line is bent midway into a pair of clo

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