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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Schmitt; Jonathan
Address:
Bloomington, MN
No. of patents:
8
Patents:












Patent Number Title Of Patent Date Issued
6130556 Integrated circuit I/O buffer with 5V well and passive gate voltage October 10, 2000
An integrated circuit buffer includes a core output terminal, a pad terminal, a pad pull-down transistor, a pad pull-up transistor, a pull-down control circuit and a pull-up control circuit. The pad pull-down transistor and the pad pull-up transistor are coupled to the pad terminal a
6118303 Integrated circuit I/O buffer having pass gate protection with RC delay September 12, 2000
An integrated circuit I/O buffer has an output driver. The output driver includes first, second and third voltage supply terminals and a pad terminal. A pad pull-up transistor is coupled in series between the first voltage supply terminal and the pad terminal and has a pull-up control
6028449 Integrated circuit I/O buffer having pull-up to voltages greater than transistor tolerance February 22, 2000
An integrated circuit having a DC current test function operates at a core supply voltage and interfaces at an input-output (I/O) supply voltage. The I/O supply voltage is greater than the core supply voltage. The integrated circuit includes a buffer, a voltage level shifting circuit and
6005413 5V tolerant PCI I/O buffer on 2.5V technology December 21, 1999
A tri-state input-output (I/O) buffer which includes a core terminal, a pad terminal and an enable terminal. A pad pull-down transistor and pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. A pull-down control circuit i
5977574 High density gate array cell architecture with sharing of well taps between cells November 2, 1999
An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at t
5966030 Output buffer with regulated voltage biasing for driving voltages greater than transistor tolera October 12, 1999
An output driver circuit includes first and second supply terminals, first and second complementary data terminals and an output terminal. A pull-up transistor is coupled between the first supply terminal and the output terminal and has a first control terminal. A pull-down transistor is
5963057 Chip level bias for buffers driving voltages greater than transistor tolerance October 5, 1999
An integrated circuit includes a core region and an input-output (I/O) region which has an I/O slot and a voltage supply slot. First and second voltage supply buses and a bias voltage bus extend along the I/O region through the I/O slot and the voltage supply slot. A bias voltage generat
5900750 5V output driver on 2.5V technology May 4, 1999
An output driver for an integrated circuit. The output driver includes a core data terminal, a pad terminal, a pull-down transistor and a pull-up transistor. The pull-down and pull-up transistors are coupled to the pad terminal and have pull-down and pull-up control terminals, respective










 
 
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