| Patent Number |
Title Of Patent |
Date Issued |
| 7496877 |
Electrostatic discharge failure avoidance through interaction between floorplanning and power ro |
February 24, 2009 |
| An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/ou |
| 7234124 |
Method and apparatus for performing power routing on a voltage island within an integrated circu |
June 19, 2007 |
| A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N-1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second |
| 6861753 |
Method and apparatus for performing power routing on a voltage island within an integrated circu |
March 1, 2005 |
| A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N-1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second |
| 6725439 |
Method of automated design and checking for ESD robustness |
April 20, 2004 |
| A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located |
| 6631502 |
Method of analyzing integrated circuit power distribution in chips containing voltage islands |
October 7, 2003 |
| A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: an |
| 5631842 |
Parallel approach to chip wiring |
May 20, 1997 |
| In any of the post-global physical design phases an integrated circuit chip is wired in parallel. The chip is first divided into adjacent bays with rough wiring coordinates from the global wiring phase. Next the bays are grouped into bay groups, with each bay group containing a contiguou |
