| Patent Number |
Title Of Patent |
Date Issued |
| 7580289 |
Discharge circuit for a word-erasable flash memory device |
August 25, 2009 |
| A non-volatile memory device is proposed. The memory device includes a plurality of blocks of memory cells, each block having a common biasing node for all the memory cells of the block, biasing means for providing a biasing voltage, and selection means for selectively applying the biasi |
| 6980458 |
Sensing circuit for ferroelectric non-volatile memories |
December 27, 2005 |
| A circuit for sensing a ferroelectric non-volatile information storage unit comprises a pre-charge circuit for applying a prescribed pre-charge voltage to a storage capacitor of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the st |
| 6930907 |
FeRAM semiconductor memory |
August 16, 2005 |
| A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local |
| 6909626 |
Method and related circuit for accessing locations of a ferroelectric memory |
June 21, 2005 |
| A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective |
| 6885574 |
Low fatigue sensing method and circuit for ferroelectric non-volatile storage units |
April 26, 2005 |
| A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method. The method comprises the steps of: making a voltage applied across the two |
| 6795330 |
Method of reading and restoring data stored in a ferroelectric memory cell |
September 21, 2004 |
| A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroe |
