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Inventor: Sayah; John Youssef
Address: North Tarrytown, NY
No. of patents: 2
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 5793641 |
Method and apparatus for placing and detecting prewire blockages of library cells |
August 11, 1998 |
| A method and apparatus for detecting valid placement of library cells on chip images or hierarchy design images may be accomplished by determining a periodic pattern of the chip image, or hierarchical image. Once the repetitive pattern is recognized, this pattern is represented by a bina |
| 5731985 |
Chip sizing for hierarchical designs |
March 24, 1998 |
| A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning proc |
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