| Patent Number |
Title Of Patent |
Date Issued |
| 8144817 |
High-precision signal detection for high-speed receiver |
March 27, 2012 |
| In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to th |
| 8081715 |
Device and method for sampling based on matched filtering |
December 20, 2011 |
| A circuit that reduces the effect of noise in a receiver that includes a plurality of filters and a plurality of samplers. The plurality of filters are configured discreetly filter a digital signal to form a plurality of filtered signals. The plurality of samplers are configured to s |
| 7949078 |
High-precision signal detection for high-speed receiver |
May 24, 2011 |
| In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to th |
| 7643583 |
High-precision signal detection for high-speed receiver |
January 5, 2010 |
| In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to th |
| 7551897 |
Method and apparatus for performing transmit pre-emphasis |
June 23, 2009 |
| A pre-emphasis circuit and methods are provided. The circuit includes a first amplifier and a second amplifier. The first amplifier contains M first driver cells and is operable to amplify a signal. The second amplifier contains P second driver cells and is operable to amplify a dela |
| 7315189 |
Retiming circuits for phase-locked loops |
January 1, 2008 |
| Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A mu |
| 7239208 |
Device and method for frequency synthesis for wireline transceivers and similar devices |
July 3, 2007 |
| A circuit, system, and method of generating multiple frequencies from a reduced number of input oscillation frequency signals including an input that receives at least two input oscillation frequency signals, each having a different phase. The circuit includes a combiner that combines |
| 7233182 |
Circuitry for eliminating false lock in delay-locked loops |
June 19, 2007 |
| A delay-locked loop (DLL) acquires correct lock when the delay line on the DLL delays a reference signal by one clock period. False lock occurs when the delay line delays the reference signal by more than one clock period. False lock may be detected by a false lock detector. The false lo |
| 7230461 |
Retiming circuits for phase-locked loops |
June 12, 2007 |
| Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A mu |
| 7227393 |
Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters |
June 5, 2007 |
| A phase locked loop (PLL) clock divider is provided that, in one implementation, includes a divider and a delay locked loop. The divider is operable to divide a reference clock signal and generate a divided clock signal. The divided clock signal has a different frequency relative to |
| 7155164 |
Method and apparatus for performing transmit pre-emphasis |
December 26, 2006 |
| A pre-emphasis circuit and methods are provided. The circuit includes a first amplifier and a second amplifier. The first amplifier is operable to amplify a signal using a first amplifier current, and the second amplifier is operable to amplify a delayed version of the signal using a |
