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Inventor: Satou; Tomio
Address: Nagoya, JP
No. of patents: 2
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 5580432 |
Jig for electroplating lead pins of an integrated circuit package |
December 3, 1996 |
| Disclosed is a method of producing an integrated circuit package, wherein portions of the package are electroplated by getting a direct electrical connection with each of lead pins joined to a package substrate. The electrical connection is obtained by force-fitting each of the lead pins |
| 5459102 |
Method of electroplating lead pins of integrated circuit package |
October 17, 1995 |
| Disclosed is a method of producing an integrated circuit package, wherein portions of The package are electroplated by getting a direct electrical connection with each of lead pins joined to a package substrate. The electrical connection is obtained by force-fitting each of the lead pins |
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