Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Satou; Tomio
Address:
Nagoya, JP
No. of patents:
2
Patents:












Patent Number Title Of Patent Date Issued
5580432 Jig for electroplating lead pins of an integrated circuit package December 3, 1996
Disclosed is a method of producing an integrated circuit package, wherein portions of the package are electroplated by getting a direct electrical connection with each of lead pins joined to a package substrate. The electrical connection is obtained by force-fitting each of the lead pins
5459102 Method of electroplating lead pins of integrated circuit package October 17, 1995
Disclosed is a method of producing an integrated circuit package, wherein portions of The package are electroplated by getting a direct electrical connection with each of lead pins joined to a package substrate. The electrical connection is obtained by force-fitting each of the lead pins










 
 
  Recently Added Patents
Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts
Method and system for remapping processing elements in a pipeline of a graphics processing unit
Optoelectronic devices and a method for producing the same
Statistical identification of instances during reconciliation process
Method and device for generating low-jitter clock
High-performance AHCI interface
Floor standing rack
  Randomly Featured Patents
Implant device
Computer generated image for a display panel or screen
Stroke dependent damping
Split-resonator integrated-post MEMS gyroscope
Apparatus, methods and articles for internegative color balancing
Device for generating flue gas to drive a gas turbine
Process for fabricating a semiconductor device
Display screen with graphical user interface
Bottle pourer
Use of a kinase inhibitor for the treatment of particular resistant tumors