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Inventor:
Sasaki; Masakazu
Address:
Tokyo, JP
No. of patents:
6
Patents:












Patent Number Title Of Patent Date Issued
6069389 Semiconductor non-volatile memory device having floating gate type field effect transistors for May 30, 2000
A semiconductor flash memory device includes floating gate type field effect transistors serving as memory cells, field effect transistors for forming peripheral circuits and bipolar transistors for forming other peripheral circuits expected to drive heavy load at high speed, and both
6027991 Method of making a silicide semiconductor device with junction breakdown prevention February 22, 2000
A method of making a semiconductor device includes a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate having an opening leading to the impurity doped region, a polycrystalline silicon la
5911105 Flash memory manufacturing method June 8, 1999
A flash memory manufacturing method according to the present invention comprising the steps of: forming a memory cell formation region, one conductivity type MOS transistor formation region and an MOS transistor formation region opposite in conductivity type to the one conductivity t
5701029 Semiconductor having polycrystalline silicon sandwiched by semiconductor substrate and metal sil December 23, 1997
In a semiconductor device including a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on t
5366907 Method of fabricating a BI-CMOS integrated circuit device November 22, 1994
The invention provides a novel method of fabricating a semiconductor integrated circuit device involving a bipolar transistor having a collector contact with side-wall oxide films. After forming an active base region, an oxide film is formed on an entire surface of the device by a va
5081058 Method of manufacturing an insulated gate field effect transistor allowing precise control of op January 14, 1992
An insulated gate field effect transistor surrounded by a field silicon oxide layer which is at least partially embedded in a silicon substrate, is disclosed. A pair of silicon oxide layers thinner than the field silicon oxide layer and thicker than the gate insulating film are formed










 
 
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