| Patent Number |
Title Of Patent |
Date Issued |
| 7280420 |
Data compression read mode for memory testing |
October 9, 2007 |
| Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data val |
| 7277311 |
Flash cell fuse circuit |
October 2, 2007 |
| Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the |
| 7180803 |
Data compression read mode for memory testing |
February 20, 2007 |
| Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data val |
| 7113435 |
Data compression read mode for memory testing |
September 26, 2006 |
| Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data val |
| 7002828 |
Flash cell fuse circuit |
February 21, 2006 |
| Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the |
| 6930936 |
Data compression read mode for memory testing |
August 16, 2005 |
| Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data val |
| 6909641 |
Flash memory sector tagging for consecutive sector erase or bank erase |
June 21, 2005 |
| A memory device includes an array of flash memory cells organized as a plurality of addressable sectors, control circuitry for controlling operations on the array of flash memory cells, and a plurality of sector tagging blocks, with each sector tagging block being associated with one |
| 6845029 |
Flash cell fuse circuit |
January 18, 2005 |
| Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the |
| 6717862 |
Flash memory sector tagging for consecutive sector erase or bank erase |
April 6, 2004 |
| Methods and apparatus to facilitate erasure of multiple sectors of a memory device without the need for externally-supplied erase potentials are advantageous for device testing. During a scan of sector addresses, sector tagging blocks of a memory device provide an output signal to a writ |
| 6654272 |
Flash cell fuse circuit |
November 25, 2003 |
| Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the |
| 6584035 |
Supply noise reduction in memory device column selection |
June 24, 2003 |
| Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for |
| 6262914 |
Flash memory segmentation |
July 17, 2001 |
| Segmentation of FLASH Memory arrays allows the global and local bit lines to be isolated, greatly reducing global bit line capacitance, reducing bit line stress, and eliminating boot block disturb effects. Reduction in bit line capacitance also results in fast access time greatly improvi |
| 6191976 |
Flash memory margin mode enhancements |
February 20, 2001 |
| FLASH Memory sense amplifier reference circuit with weighted dummy loads is used to balance and bias the sense amplifier during erasing, programming, and verification such that the resulting robust stored logic states can meet more stringent pass-fail verify "1" or verify "0" tests. Prog |
| 6118706 |
Flash memory block or sector clear operation |
September 12, 2000 |
| FLASH Memory hardware Block or sector Clear Operation using a single block or sector operation without using "byte-mode" processing is described. This hardware Block or sector Clear operation does not use avalanche injection, and has several distinct advantages, including programming |
| 5874849 |
Low voltage, high current pump for flash memory |
February 23, 1999 |
| A charge pump 1 for operation in an integrated circuit having a power source Vdd. The pump is made of a plurality of pump cells 10 connected together. Each pump cell includes an inverter 50 having a port 42 to receive a negative bias input, a port 44 to receive a positive bias input, |
| 5717634 |
Programmable and convertible non-volatile memory array |
February 10, 1998 |
| A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 |
| 5715195 |
Programmable memory verify "0" and verify "1" circuit and method |
February 3, 1998 |
| A method for automatically detecting and correcting the underprogramming of a memory cell 10 in a non-volatile, progrommable memory array 1, the array having a plurality of such cells, each such cell being programmable by a progromming step that stores charge therein and being erasable b |
| 5703807 |
EEPROM with enhanced reliability by selectable V.sub.PP for write and erase |
December 30, 1997 |
| A circuit and method for generating an erasure voltage and a programming voltage for an EEPROM array, the cells of the EEPROM array being capable of erasure and programming. A signal having an increasing voltage is generated. That signal is monitored, and the increase in voltage of said |
