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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Sandhu; Gurtej S.
Address:
Boise, ID
No. of patents:
751
Patents:


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Patent Number Title Of Patent Date Issued
RE43025 Mixed composition interface layer and method of forming December 13, 2011
An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first che
RE40114 Tungsten silicide (WSIX) deposition process for semiconductor manufacture February 26, 2008
A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the substrate using a (CVD) process with a silane source gas followed by deposition of the tungsten silicide film with a dichlor
RE39547 Method and apparatus for endpointing mechanical and chemical-mechanical polishing of substrates April 3, 2007
An apparatus and method for stopping mechanical and chemical-mechanical polishing of a substrate at a desired endpoint. In one embodiment, a polishing machine has a platen, a polishing pad positioned on the platen, and a polishing medium located at a planarizing surface of the polishing
RE39195 Polishing pad refurbisher for in situ, real-time conditioning and cleaning of a polishing pad us July 18, 2006
A pad refurbisher that provides in situ, real-time conditioning and/or cleaning of a polishing surface on a polishing pad used in chemical-mechanical polishing of a semiconductor wafer and other microelectronic substrates. The pad refurbisher has a body adapted for attachment to a wa
RE36050 Method for repeatable temperature measurement using surface reflectivity January 19, 1999
A method is disclosed for continuously measuring the temperature of a semiconductor substrate in a chamber is disclosed. The first step of the method involves providing a substantially clean semiconductor substrate having a layer a reflective surface thereon into a chamber. A film is
RE35785 Low-pressure chemical vapor deposition process for depositing high-density highly-conformal, tit May 5, 1998
A low-pressure chemical vapor deposition process is disclosed for creating high-density, highly-conformal titanium nitride films which have very low bulk resistivity, and which provide excellent step coverage. The process utilizes a metal-organic compound, tetrakis-dialkylamido-titanium
8581224 Memory cells November 12, 2013
Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative t
8564039 Semiconductor devices including gate structures comprising colossal magnetocapacitive materials October 22, 2013
Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical current flow through the channel region between a source and a drain. The c
8563228 Methods of forming patterns on substrates October 22, 2013
A method of forming a pattern on a substrate includes forming spaced first features over a substrate. The spaced first features have opposing lateral sidewalls. Material is formed onto the opposing lateral sidewalls of the spaced first features. That portion of such material which is
8300454 Spin torque transfer memory cell structures and methods October 30, 2012
Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic
8288818 Devices with nanocrystals and methods of formation October 16, 2012
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose
8282999 Spin-on film processing using acoustic radiation pressure October 9, 2012
An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure to alter the liquid topography. Other apparatus and processes are disclosed.
8278167 Method and structure for integrating capacitor-less memory cell with logic October 2, 2012
Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits
8273643 Diodes, and methods of forming diodes September 25, 2012
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the
8273634 Methods of fabricating substrates September 25, 2012
A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and
8268692 Non-volatile memory cell devices and methods September 18, 2012
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectr
8268543 Methods of forming patterns on substrates September 18, 2012
A method of forming a pattern on a substrate includes forming spaced first features over a substrate. The spaced first features have opposing lateral sidewalls. Material is formed onto the opposing lateral sidewalls of the spaced first features. That portion of such material which is
8258034 Charge-trap based memory September 4, 2012
Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical openi
8256695 Method for purification of semiconducting single wall nanotubes September 4, 2012
A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive carbon nanotubes under conditions to cause the metallic carbon nanotubes to be digested or to decompose so that they may be
8247302 Methods of fabricating substrates August 21, 2012
A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater
8228730 Memory cell structures and methods July 24, 2012
Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source
8227313 One-transistor composite-gate memory July 24, 2012
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be
8223539 GCIB-treated resistive device July 17, 2012
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a low
8222127 Methods of forming structures having nanotubes extending between opposing electrodes and structu July 17, 2012
A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a di
8207576 Pitch reduced patterns relative to photolithography features June 26, 2012
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography us
8207570 Semiconductor constructions June 26, 2012
Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates
8207563 Integrated circuitry June 26, 2012
A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure compris
8207557 Cross-point memory structures June 26, 2012
Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the
8207016 Methods of cooling semiconductor dies June 26, 2012
The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes meth
8199556 Methods of reading and using memory cells June 12, 2012
Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration
8198172 Methods of forming integrated circuits using donor and acceptor substrates June 12, 2012
Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each leve
8174061 Floating-gate structure with dielectric component May 8, 2012
Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate.
8173034 Methods of utilizing block copolymer to form patterns May 8, 2012
Some embodiments include methods of utilizing block copolymer to form patterns between weirs. The methods may utilize liners along surfaces of the weirs to compensate for partial-width segments of the patterns in regions adjacent the weirs. Some embodiments include methods in which s
8164081 Memory devices and formation methods April 24, 2012
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite condu
8163355 Formation of carbon-containing material April 24, 2012
A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp.sup.2 bonds, and accelerating the clusters. A surface of a substrate is irradiated with the clusters. A material is formed on the surface using the carbon from the molecules.
8148222 Cross-point diode arrays and methods of manufacturing cross-point diode arrays April 3, 2012
Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lin
8133664 Methods of forming patterns March 13, 2012
Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the
8129289 Method to deposit conformal low temperature SiO2 March 6, 2012
Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring t
8123968 Multiple deposition for integration of spacers in pitch multiplication process February 28, 2012
Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precurso
8119535 Pitch reduced patterns relative to photolithography features February 21, 2012
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography us
8114573 Topography based patterning February 14, 2012
A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed lay
8093658 Electronic device with asymmetric gate strain January 10, 2012
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing
8088293 Methods of forming reticles configured for imprint lithography January 3, 2012
The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a
8084142 Methods of forming conductive contacts to source/drain regions and methods of forming local inte December 27, 2011
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor inc
8080460 Methods of forming diodes December 20, 2011
Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing side
8067803 Memory devices, transistor devices and related methods November 29, 2011
A memory device and method of making the memory device. The memory device comprises a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first
8063454 Semiconductor structures including a movable switching element and systems including same November 22, 2011
Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switchin
8058130 Method of forming a nitrogen-enriched region within silicon-oxide-containing masses November 15, 2011
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to
8057686 Nanotube separation methods November 15, 2011
A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a deposition rate is greater than on another nanotube in the mixture lacking the defect. The method includes removing the tagged
8052075 Method for purification of semiconducting single wall nanotubes November 8, 2011
A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive carbon nanotubes under conditions to cause the metallic carbon nanotubes to be digested or to decompose so that they may be
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