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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Salapura; Valentina
Address:
Chappaqua, NY
No. of patents:
49
Patents:












Patent Number Title Of Patent Date Issued
8255638 Snoop filter for filtering snoop requests August 28, 2012
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter dev
8230433 Shared performance monitor in a multiprocessor system July 24, 2012
A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the
8135917 Method and apparatus for filtering snoop requests using stream registers March 13, 2012
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one
8127078 High performance unaligned cache access February 28, 2012
A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with the target cache
8103836 Snoop filtering system in a multiprocessor system January 24, 2012
A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter un
8103832 Method and apparatus of prefetching streams of varying prefetch depth January 24, 2012
Method and apparatus of prefetching streams of varying prefetch depth dynamically changes the depth of prefetching so that the number of multiple streams as well as the hit rate of a single stream are optimized. The method and apparatus in one aspect monitor a plurality of load reque
8036243 Single chip protocol converter October 11, 2011
A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process
8015364 Method and apparatus for filtering snoop requests using a scoreboard September 6, 2011
An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more "scoreboard" data structures that make snoop dete
7957288 Method and system of efficient packet reordering June 7, 2011
A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list,
7917729 System on chip IC with subsystem of multiple processing cores switch coupled to network protocol March 29, 2011
A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each proce
7908439 Method and apparatus for efficient replacement algorithm for pre-fetcher oriented data cache March 15, 2011
Disclosed are a method and apparatus for replacing pre-fetched data in a pre-fetch cache. In one embodiment, each line of the pre-fetch cache will be accessed at most M times. A line accessed M times can be evicted from the cache without any performance loss. In this embodiment, a counte
7877759 System for efficient performance monitoring of a large number of simultaneous events January 25, 2011
A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count
7877551 Programmable partitioning for high-performance coherence domains in a multiprocessor system January 25, 2011
A multiprocessor computing system and a method of logically partitioning a multiprocessor computing system are disclosed. The multiprocessor computing system comprises a multitude of processing units, and a multitude of snoop units. Each of the processing units includes a local cache
7836260 Low complexity speculative multithreading system based on unmodified microprocessor core November 16, 2010
A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memo
7827391 Method and apparatus for single-stepping coherence events in a multiprocessor system under softw November 2, 2010
An apparatus and method are disclosed for single-stepping coherence events in a multiprocessor system under software control in order to monitor the behavior of a memory coherence mechanism. Single-stepping coherence events in a multiprocessor system is made possible by adding one or mor
7793038 System and method for programmable bank selection for banked memory subsystems September 7, 2010
A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first
7788334 Multiple node remote messaging August 31, 2010
A method for passing remote messages in a parallel computer system formed as a network of interconnected compute nodes includes that a first compute node (A) sends a single remote message to a remote second compute node (B) in order to control the remote second compute node (B) to send
7782995 Low latency counter event indication August 24, 2010
A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device
7761687 Ultrascalable petaflop parallel supercomputer July 20, 2010
A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnecte
7688931 Space and power efficient hybrid counters array March 30, 2010
A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to
7680971 Method and apparatus for granting processors access to a resource March 16, 2010
An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or more request signals
7669012 Insertion of coherence requests for debugging a multiprocessor February 23, 2010
A method and system are disclosed to insert coherence events in a multiprocessor computer system, and to present those coherence events to the processors of the multiprocessor computer system for analysis and debugging purposes. The coherence events are inserted in the computer syste
7620756 Method and apparatus for updating wide storage array over a narrow bus November 17, 2009
A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m<n) for updating a wide data storage array. The apparatus includes: a staging latch accommodating m bits, e.g., 32 bits; control circuitry for depositing the m bits of data from a data b
7617366 Method and apparatus for filtering snoop requests using mulitiple snoop caches November 10, 2009
A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered
7603524 Method and apparatus for filtering snoop requests using multiple snoop caches October 13, 2009
A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port is a snoop cache filt
7603523 Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture October 13, 2009
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter dev
7532700 Space and power efficient hybrid counters array May 12, 2009
A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to
7477644 Method and system of efficient packet reordering January 13, 2009
A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list,
7461383 Method and apparatus for efficient performance monitoring of a large number of simultaneous even December 2, 2008
A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count
7426253 Low latency counter event indication September 16, 2008
A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device
7412588 Network processor system on chip with bridge coupling protocol converting multiprocessor macro c August 12, 2008
A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted packets of a second p
7404041 Low complexity speculative multithreading system based on unmodified microprocessor core July 22, 2008
A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memo
7392351 Method and apparatus for filtering snoop requests using stream registers June 24, 2008
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one
7386685 Method and apparatus for filtering snoop requests using multiple snoop caches June 10, 2008
A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port is a snoop cache filt
7386684 Method and apparatus for detecting a cache wrap condition June 10, 2008
A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered
7386683 Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture June 10, 2008
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter dev
7383397 Method and apparatus for filtering snoop requests using a scoreboard June 3, 2008
An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more "scoreboard" data structures that make snoop dete
7380071 Snoop filtering system in a multiprocessor system May 27, 2008
A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter un
7373462 Snoop filter for filtering snoop requests May 13, 2008
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter dev
7353362 Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC sy April 1, 2008
A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each proce
7350027 Architectural support for thread level speculative execution March 25, 2008
A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or existing caches on the L1, L2 or L3 level. Architecture support for thread speculative executi
7243333 Method and apparatus for creating and executing integrated executables in a heterogeneous archit July 10, 2007
The present invention provides a compilation system for compiling and linking an integrated executable adapted to execute on a heterogeneous parallel processor architecture. The compiler and linker compile different segments of the source code for a first and second processor archite
7225431 Method and apparatus for setting breakpoints when debugging integrated executables in a heteroge May 29, 2007
The present invention provides inserting and deleting a breakpoint in a parallel processing system. A breakpoint is inserted in a module loaded into the execution environment of an attached processor unit. The breakpoint can be inserted directly. Furthermore, the unloaded image of th
7222332 Method and apparatus for overlay management within an integrated executable for a heterogeneous May 22, 2007
The present invention provides for creating and employing code and data partitions in a heterogeneous environment. This is achieved by separating source code and data into at least two partitioned sections and at least one unpartitioned section. Generally, a partitioned section is target
7213123 Method and apparatus for mapping debugging information when debugging integrated executables in May 1, 2007
The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping table, wherein the mapping table is read by the dynamic debugger.
7200840 Method and apparatus for enabling access to global data by a plurality of codes in an integrated April 3, 2007
In the present invention, global information is passed from a first execution environment to a second execution environment, wherein both the first and second processor units comprise separate memories. The global variable is transferred through the invocation of a memory flow contro
7032101 Method and apparatus for prioritized instruction issue queue in a processor April 18, 2006
An apparatus and method in a high performance processor for issuing instructions, comprising; a classification logic for sorting instructions in a number of priority categories, a plurality of instruction queues storing the instruction of differing priorities, and a issue logic selec
7003597 Dynamic reallocation of data stored in buffers based on packet size February 21, 2006
A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for
6948082 Method and apparatus for software-assisted thermal management for electronic systems September 20, 2005
In a computer system, a device for measuring power dissipation (e.g., using on-die thermal sensors) is linked to both a hardware-based thermal management solution and with a means for causing a notification event to software, so that, initially, the operating system software and/or the










 
 
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