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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Safford; Kevin David
Address:
Fort Collins, CO
No. of patents:
24
Patents:












Patent Number Title Of Patent Date Issued
7725899 Method and apparatus for communicating information between lock stepped processors May 25, 2010
An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic. The apparatus further
7398419 Method and apparatus for seeding differences in lock-stepped processors July 8, 2008
An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode. Each of the two or more processors comprise a processor-specific resource operable to seed the dif
7370232 Method and apparatus for recovery from loss of lock step May 6, 2008
An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operatin
7343479 Method and apparatus for implementing two architectures in a chip March 11, 2008
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstruc
7296181 Lockstep error signaling November 13, 2007
Techniques are disclosed, for use in a computer system including a plurality of processing units coupled over a system fabric, to identify a lockstep error associated with a first packet to be transmitted over the system fabric; set a viral indicator in the first packet to indicate the
7290169 Core-level processor lockstepping October 30, 2007
A device is provided which includes a first microprocessor core to generate a first output signal; a second microprocessor core to generate a second output signal; a switching fabric having a first input/output port; and lockstep logic, coupled between the first input/output port of
7287185 Architectural support for selective use of high-reliability mode in a computer system October 23, 2007
In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability m
7237144 Off-chip lockstep checking June 26, 2007
A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differ
7155721 Method and apparatus for communicating information between lock stepped processors December 26, 2006
An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic. The apparatus further
7139936 Method and apparatus for verifying the correctness of a processor behavioral model November 21, 2006
An apparatus verifies the correctness of a behavioral model of a microcode machine, where the microcode machine is operable in a native state and an emulated state. The apparatus includes means for producing the native state, means for producing the emulated state, and means for comparin
7100097 Detection of bit errors in maskable content addressable memories August 29, 2006
Parity and mask bit(s) are stored in a random access memory (RAM) that is coupled to a CAM. This CAM may be part of a TLB. The parity and mask bits(s) are stored in conjunction with the CAM entry write. Upon a CAM query match, the reference parity bit(s) and mask bit(s) stored at the
7085959 Method and apparatus for recovery from loss of lock step August 1, 2006
An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operatin
7003691 Method and apparatus for seeding differences in lock-stepped processors February 21, 2006
An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode, wherein each of the two or more processors comprise a processor-specific resource operable to seed the
6820190 Method and computer system for decomposing macroinstructions into microinstructions and forcing November 16, 2004
The present invention is a method for processing instructions by decomposing a macroinstruction into at least two microinstructions, executing the microinstructions in parallel, and linking the microinstructions such that they appear as though they were executed as a single functiona
6807625 Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between October 19, 2004
An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by
6789186 Method and apparatus to reduce penalty of microcode lookup September 7, 2004
A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles.
6745322 Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition June 1, 2004
A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a
6681322 Method and apparatus for emulating an instruction set extension in a digital computer system January 20, 2004
Methods for emulating an instruction set extension, comprising providing data to be operated upon, executing a first instruction with respect to a first portion of the data without committing the results of the first executed instruction, if no unmasked exceptions occur with respect to t
6668315 Methods and apparatus for exchanging the contents of registers December 23, 2003
A processor based computer system having dependency checking logic and a register stack, wherein the system overrides the dependency logic such that move instructions associated with the stack registers may be executed in parallel. The system operates such that it can be determined wheth
6643800 Method and apparatus for testing microarchitectural features by using tests written in microcode November 4, 2003
An apparatus and a method of testing computer microarchitectures has a test writer create a test sequence written directly in microinstructions (both native-mode and emulation-only microinstructions). The microinstruction sequence is then inserted into a reprogrammable microcode storage,
6625759 Method and apparatus for verifying the fine-grained correctness of a behavioral model of a centr September 23, 2003
A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by a
6618801 Method and apparatus for implementing two architectures in a chip using bundles that contain mic September 9, 2003
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstruc
6609247 Method and apparatus for re-creating the trace of an emulated instruction set when executed on h August 19, 2003
A method and an apparatus for re-creating a trace of instructions from an emulated instruction set when running on hardware optimized for a different instruction set, such as IA-32 instructions running on an IA-64 machine, are disclosed. An execution trace buffer is created that main
6542862 Determining register dependency in multiple architecture systems April 1, 2003
An apparatus and method for determining register dependency in multiple architecture system. The system includes a microprocessor emulating an emulated instruction set using a native instruction set where the microprocessor contains at least one register. An execution engine provides










 
 
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