| Patent Number |
Title Of Patent |
Date Issued |
| 7467286 |
Executing partial-width packed data instructions |
December 16, 2008 |
| A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit |
| 7395302 |
Method and apparatus for performing horizontal addition and subtraction |
July 1, 2008 |
| A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data |
| 7392275 |
Method and apparatus for performing efficient transformations with horizontal addition and subtr |
June 24, 2008 |
| A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data |
| 7366881 |
Method and apparatus for staggering execution of an instruction |
April 29, 2008 |
| A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers re |
| 7216138 |
Method and apparatus for floating point operations and format conversion operations |
May 8, 2007 |
| A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format.Numbers are stored in the floating point format in a register of a |
| 6970994 |
Executing partial-width packed data instructions |
November 29, 2005 |
| A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to st |
| 6961845 |
System to perform horizontal additions |
November 1, 2005 |
| A method and apparatus for including in a processor instructions for performing intra-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data. The processor performs operations on data elements in the fir |
| 6925553 |
Staggering execution of a single packed data instruction using the same circuit |
August 2, 2005 |
| A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The m |
| 6721866 |
Unaligned memory operands |
April 13, 2004 |
| A method of obtaining an operand from a memory device includes reading a first operand from a first location in a memory device, the first operand including part of the operand specified by an instruction, shifting the first operand by a first shift amount, reading a second data operand |
| 6694426 |
Method and apparatus for staggering execution of a single packed data instruction using the same |
February 17, 2004 |
| A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers re |
| 6687810 |
Method and apparatus for staggering execution of a single packed data instruction using the same |
February 3, 2004 |
| A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers re |
| 6502115 |
Conversion between packed floating point data and packed 32-bit integer data in different archit |
December 31, 2002 |
| A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is |
| 6480868 |
Conversion from packed floating point data to packed 8-bit integer data in different architectur |
November 12, 2002 |
| A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating po |
| 6425073 |
Method and apparatus for staggering execution of an instruction |
July 23, 2002 |
| A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers re |
| 6418529 |
Apparatus and method for performing intra-add operation |
July 9, 2002 |
| Method and apparatus for including in a processor, instructions for performing intra-add operations on packed data. In one embodiment, an execution unit is coupled to a storage area. The storeage area has stored therein a first packed data operand and a second packed data operand. The |
| 6317824 |
Method and apparatus for performing integer operations in response to a result of a floating poi |
November 13, 2001 |
| A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. |
| 6292815 |
Data conversion between floating point packed format and integer scalar format |
September 18, 2001 |
| A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is |
| 6266769 |
Conversion between packed floating point data and packed 32-bit integer data in different archit |
July 24, 2001 |
| A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is |
| 6263426 |
Conversion from packed floating point data to packed 8-bit integer data in different architectur |
July 17, 2001 |
| A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating po |
| 6247116 |
Conversion from packed floating point data to packed 16-bit integer data in different architectu |
June 12, 2001 |
| A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating po |
| 6230257 |
Method and apparatus for staggering execution of a single packed data instruction using the same |
May 8, 2001 |
| A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers re |
| 6230253 |
Executing partial-width packed data instructions |
May 8, 2001 |
| A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, |
| 6122725 |
Executing partial-width packed data instructions |
September 19, 2000 |
| A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming u |
| 6041404 |
Dual function system and method for shuffling packed data elements |
March 21, 2000 |
| An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accesse |
| 5995122 |
Method and apparatus for parallel conversion of color values from a single precision floating po |
November 30, 1999 |
| A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to |
