| Patent Number |
Title Of Patent |
Date Issued |
| 6490190 |
Memory cell configuration, magnetic ram, and associative memory |
December 3, 2002 |
| A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense |
| 6417043 |
Memory cell configuration and fabrication method |
July 9, 2002 |
| Resistors are connected between word lines and bit lines running transversely with respect thereto. The resistors have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier which regulates the potential on the respective bit line |
| 6362502 |
DRAM cell circuit |
March 26, 2002 |
| A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region |
| 6337247 |
Method of producing a vertical MOS transistor |
January 8, 2002 |
| A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantatio |
| 6320447 |
Circuit configuration with single-electron components, and operating method |
November 20, 2001 |
| The circuit configuration has at least five single-electron transistors, three of which are connected via a second main node and a third main node between a first main node and an output. The fourth single-electron transistor is connected between the second main node and a first supply |
| 6300198 |
Method for producing a vertical MOS-transistor |
October 9, 2001 |
| In order to produce a vertical MOS transistor with optimized gate overlap capacitances, a mesa structure is formed with an upper source/drain region, a channel region and a lower source/drain region. With the aid of chemical/mechanical polishing, an insulation structure is formed which |
| 6229169 |
Memory cell configuration, method for fabricating it and methods for operating it |
May 8, 2001 |
| A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the |
| 6038164 |
SRAM cell configuration and method for its fabrication |
March 14, 2000 |
| The SRAM cell configuration has at least six transistors in each memory cell. Four of the transistors form a flip-flop and they are arranged at the corners of a quadrilateral. The flip-flop is driven by two of the transistors, which are disposed so as to adjoin diagonally opposite co |
| 6037209 |
Method for producing a DRAM cellular arrangement |
March 14, 2000 |
| The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected |
| 5998261 |
Method of producing a read-only storage cell arrangement |
December 7, 1999 |
| An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. |
| 5973373 |
Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of differe |
October 26, 1999 |
| A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement |
| 5920778 |
Read-only memory cell arrangement and method for its production |
July 6, 1999 |
| In a read-only memory cell arrangement having first memory cells which contain a vertical MOS transistor, and having second memory cells which do not contain vertical MOS transistors, the memory cells are arranged along opposite flanks of strip-shaped parallel insulation trenches (16). T |
| 5844834 |
Single-electron memory cell configuration |
December 1, 1998 |
| Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent |
| 5744393 |
Method for production of a read-only-memory cell arrangement having vertical MOS transistors |
April 28, 1998 |
| A method for production of a read-only-memory cell arrangement having vertical MOS transistors is provided. In order to produce a read-only-memory cell arrangement which has first memory cells having a vertical MOS transistor and second memory cells which do not have a vertical MOS t |
| 5600162 |
DRAM-type memory cell arrangement on a substrate |
February 4, 1997 |
| In a DRAM cell arrangement, two memory cells which include an MOS transistor and a memory element are constructed in each case as a transistor pair (10) whose source areas are connected to one another and to a bitline (11). The MOS transistors have a linear arrangement of the drain a |
| 5496757 |
Process for producing storage capacitors for DRAM cells |
March 5, 1996 |
| To produce storage capacitors for DRAM cells, dummies (81) of SiO.sub.2 which are disposed in accordance with the negative pattern of the storage node arrangement (91) are formed using auxiliary layers of SiO.sub.2 and polysilicon. The storage nodes (91) are formed, by depositing a doped |
| 5432115 |
Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transi |
July 11, 1995 |
| To make a contact between a capacitor electrode (13) disposed in a trench (11) and an MOS transistor source/drain region disposed outside the trench, a shallow etching is carried out in a self-aligned manner with respect to a field-oxide region insulating the MOS transistor by producing |
