| Patent Number |
Title Of Patent |
Date Issued |
| 6352894 |
Method of forming DRAM cell arrangement |
March 5, 2002 |
| A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/dra |
| 6307422 |
Circuit configuration having single-electron components, a method for its operation and use of t |
October 23, 2001 |
| At least one single-electron transistor is provided in a circuit configuration having single-electron components, and is connected between a first main node and a second main node. The first main node is capacitively connected between a first operating voltage connection and a second |
| 6274431 |
Method for manufacturing an integrated circuit arrangement having at least one MOS transistor |
August 14, 2001 |
| An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the cha |
| 6184045 |
Method for DRAM cell arrangement and method for its production |
February 6, 2001 |
| A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis o |
| 6180458 |
Method of producing a memory cell configuration |
January 30, 2001 |
| A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed |
| 6147376 |
DRAM cell arrangement and method for its production |
November 14, 2000 |
| A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis o |
| 6066876 |
Integrated circuit arrangement having at least one MOS transistor manufactured by use of a plana |
May 23, 2000 |
| An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the cha |
| 6060911 |
Circuit arrangement with at least four transistors, and method for the manufacture thereof |
May 9, 2000 |
| In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at lea |
| 6044009 |
DRAM cell arrangement and method for its production |
March 28, 2000 |
| A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/dra |
| 5821591 |
High density read only memory cell configuration and method for its production |
October 13, 1998 |
| A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed |
| 5817552 |
Process of making a dram cell arrangement |
October 6, 1998 |
| For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of whi |
| 5736761 |
DRAM cell arrangement and method for its manufacture |
April 7, 1998 |
| The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capa |
| 5612233 |
Method for manufacturing a single electron component |
March 18, 1997 |
| In a method for manufacturing a single electron component in MOS technique, an active zone provided with a gate dielectric is defined in a silicon substrate. With assistance of a fine-structuring method, particularly with electron beam lithography, a first gate level is generated with fi |
| 5540977 |
Microelectronic component |
July 30, 1996 |
| A microelectronic component has a substrate on which a layer structure and at least two contact structures are arranged. The layer structure and the contact structures are electrically connected to one another but are electrically insulated from the substrate. The layer structure is form |
| 5385852 |
Method for manufacturing vertical MOS transistors |
January 31, 1995 |
| For manufacturing vertical MOS transistors, doped regions for a drain (11), well (3), and source (4) are formed in a vertical sequence in a substrate (1). Using a Si.sub.3 N.sub.4 mask (5), trenches (6) are etched perpendicular to the surface of the substrate (1). The trenches isolate |
