| Patent Number |
Title Of Patent |
Date Issued |
| RE39768 |
VCC pump for CMOS imagers |
August 14, 2007 |
| A CMOS imaging device which includes a charge pump connected to one or more of a reset gate, transfer gate and row select gate of sensor cells and provides gate control signals which give the imaging device an increased dynamic range charge capacity while minimizing signal leakage. A |
| 7622321 |
High dielectric constant spacer for imagers |
November 24, 2009 |
| An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and improves image lag and charge transfer efficiency. |
| 7619672 |
Retrograde well structure for a CMOS imager |
November 17, 2009 |
| A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the |
| 7618839 |
Pinned photodiode structure and method of formation |
November 17, 2009 |
| An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface |
| 7616245 |
Active pixel sensor with a diagonal active area |
November 10, 2009 |
| An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the |
| 7608870 |
Isolation trench geometry for image sensors |
October 27, 2009 |
| A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench has sidewalls and a bottom. At least one sidewall is angled less than approximately 85 |
| 7589365 |
Dual capacitor structure for imagers |
September 15, 2009 |
| CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in periphery circuits have different requirements from the capacitors used in the pixel itself. Dual stack capacitors comprising |
| 7573113 |
Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method |
August 11, 2009 |
| A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5. |
| 7563631 |
Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduc |
July 21, 2009 |
| A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed a |
| 7557024 |
Single poly CMOS imager |
July 7, 2009 |
| More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and |
| 7535042 |
Pixel cell with a controlled output signal knee characteristic response |
May 19, 2009 |
| A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have the gate profile of a transfer gate or a reset gate. The HDR transistor may be located on a side of the photodiode that is the |
| 7524695 |
Image sensor and pixel having an optimized floating diffusion |
April 28, 2009 |
| An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusio |
| 7511354 |
Well for CMOS imager and method of formation |
March 31, 2009 |
| A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second |
| 7498188 |
Contacts for CMOS imagers and method of formation |
March 3, 2009 |
| Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon r |
| 7485587 |
Method of making a semiconductor device having improved contacts |
February 3, 2009 |
| A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer |
| 7445951 |
Trench photosensor for a CMOS imager |
November 4, 2008 |
| A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photos |
| 7432543 |
Image sensor pixel having photodiode with indium pinning layer |
October 7, 2008 |
| An active pixel using a pinned photodiode with a pinning layer formed from indium is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N.sup.- region formed within a P-type region. A pinning layer formed from indium is then formed a |
| 7422924 |
Image device and photodiode structure |
September 9, 2008 |
| The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity concentration form a region surrounding at least part of the isolation region. These dopant |
| 7420233 |
Photodiode for improved transfer gate leakage |
September 2, 2008 |
| An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to e |
| 7405101 |
CMOS imager with selectively silicided gate |
July 29, 2008 |
| The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the |
| 7402451 |
Optimized transistor for imager device |
July 22, 2008 |
| An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, w |
| 7397075 |
Method and apparatus providing CMOS imager device pixel with transistor having lower threshold v |
July 8, 2008 |
| A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly |
| 7390690 |
Imager light shield |
June 24, 2008 |
| An improved imager pixel arrangement having a light shield over the pixel circuitry, but below the conductive interconnect layers of the pixel. The light shield can be a thin film of opaque (or nearly-opaque) material with openings for contacts to the underlying circuitry. An aperture in |
| 7388289 |
Local multilayered metallization |
June 17, 2008 |
| An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a function of the width. In an alternate embodiment, a metallization structure having a |
| 7388241 |
Pinned photodiode structure and method of formation |
June 17, 2008 |
| An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface |
| 7378697 |
Pinned photodiode structure and method of formation |
May 27, 2008 |
| An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface |
| 7378696 |
Pinned photodiode structure and method of formation |
May 27, 2008 |
| An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface |
| 7375026 |
Local multilayered metallization |
May 20, 2008 |
| An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a function of the width. In an alternate embodiment, a metallization structure having a |
| 7368339 |
Method and apparatus providing CMOS imager device pixel with transistor having lower threshold v |
May 6, 2008 |
| A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly |
| 7359607 |
Waveguide for thermo optic device |
April 15, 2008 |
| A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an |
| 7355229 |
Masked spacer etching for imagers |
April 8, 2008 |
| The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N.sup.+ source/drain implant and P-channel regions are then opened for P.sup.+ source/drain i |
| 7355228 |
Image sensor pixel having photodiode with multi-dopant implantation |
April 8, 2008 |
| An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N.sup.- region formed within a P-type region. The N.sup.- region is formed from an implant of arsenic and an |
| 7348613 |
CMOS imager with selectively silicided gates |
March 25, 2008 |
| The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the |
| 7345330 |
Local interconnect structure and method for a CMOS image sensor |
March 18, 2008 |
| A self-aligned silicide (salicide) process is used to form a local interconnect for a CMOS image sensor consistent with a conventional CMOS image sensor process flow. An oxide layer is deposited over the pixel array of the image sensor. Portions of the oxide layer is removed and a me |
| 7344910 |
Self-aligned photodiode for CMOS image sensor and method of making |
March 18, 2008 |
| A method for forming a photodiode that is self-aligned to a transfer gate while being compatible with a metal silicide process is disclosed. The method comprises forming a gate stack of gate oxide, polysilicon, and a sacrificial/disposable cap insulator over the polysilicon. The insulato |
| 7339217 |
High dynamic range image sensor |
March 4, 2008 |
| A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR trans |
| 7332737 |
Isolation trench geometry for image sensors |
February 19, 2008 |
| A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench has sidewalls and a bottom. At least one sidewall is angled less than approximately 85 |
| 7323353 |
Resonator for thermo optic device |
January 29, 2008 |
| A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the |
| 7312431 |
CMOS imaging for ALC and CDS |
December 25, 2007 |
| Embodiments of the invention provide pixel cells that allow both automatic light control and correlated double sampling operations. The pixel cell includes first and second photo-conversion devices that can be separately read out. For example, the second photo-conversion device can be th |
| 7279766 |
Photodiode sensor and photosensor for use in an imaging device |
October 9, 2007 |
| A multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element with an increased surface area compared to a flat |
| 7279353 |
Passivation planarization |
October 9, 2007 |
| A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process such as chemical mechanical polishing, mechanical abrasion, or etching. A spin-on-glass la |
| 7274054 |
Dual capacitor structure for imagers and method of formation |
September 25, 2007 |
| CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in periphery circuits have different requirements from the capacitors used in the pixel itself. Dual stack capacitors comprising |
| 7259413 |
High dynamic range image sensor |
August 21, 2007 |
| A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR trans |
| 7253020 |
Deuterium alloy process for image sensors |
August 7, 2007 |
| A method of alloying an image sensor is disclosed. The method comprises forming various semiconductor devices in a semiconductor substrate. Then, an insulator layer is formed over the semiconductor devices. Finally, deuterium gas is used to alloy said image sensor after the insulator |
| 7250647 |
Asymmetrical transistor for imager device |
July 31, 2007 |
| An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, w |
| 7250321 |
Method of forming a photosensor |
July 31, 2007 |
| A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photos |
| 7226803 |
Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method |
June 5, 2007 |
| A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5. |
| 7224009 |
Method for forming a low leakage contact in a CMOS imager |
May 29, 2007 |
| An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the di |
| 7214575 |
Method and apparatus providing CMOS imager device pixel with transistor having lower threshold v |
May 8, 2007 |
| A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly |
| 7211848 |
Masked spacer etching for imagers |
May 1, 2007 |
| The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N.sup.+ source/drain implant and P-channel regions are then opened for P.sup.+ source/drain i |
