| |
 |
|
|
Inventor: Reynolds; Jack
Address: Dallas, TX
No. of patents: 3
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 5407844 |
Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar t |
April 18, 1995 |
| An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to |
| 5275961 |
Method of forming insulated gate field-effect transistors |
January 4, 1994 |
| An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to |
| 5266517 |
Method for forming a sealed interface on a semiconductor device |
November 30, 1993 |
| According to the invention, a semiconductor device is provided at the face of a substrate. A layer of insulator is formed adjacent the face of substrate, layer of insulator having a window disposed therethrough. A region of epitaxially semiconductor is disposed in window informs an i |
|
|
|
