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Reohr, Jr.; Richard D.
Hillsboro, OR
No. of patents:

Patent Number Title Of Patent Date Issued
7570659 Multi-lane receiver de-skewing August 4, 2009
A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal ou
7460528 Processing data packets at a storage service module of a switch December 2, 2008
Routing a data packet of an information unit sequence includes receiving at a switch a data packet of an information unit sequence of a block storage exchange from a storage client, where the sequence is associated with a source identifier and a target identifier identifying a target. A
7382776 Performing block storage virtualization at a switch June 3, 2008
Routing a data packet includes receiving at a switch a data packet from a storage client. The data packet is associated with a destination identifier identifying a virtual target, where the virtual target is accessible by the storage client. A storage resource identifier correspondin
7190667 Link level packet flow control mechanism March 13, 2007
Some embodiments of the present invention include data network comprising a host system having a host-fabric adapter; at least one remote system; a switch fabric which interconnects said host system via said host-fabric adapter to said remote system along different physical links for dat
7088735 Processing data packets in a multiple protocol system area network August 8, 2006
Processing a data packet in a multiple protocol system area network is disclosed. A paddle card comprising a first paddle card that supports a first communication protocol or a second paddle card that supports a second communication protocol is received. The communication protocol su
7054331 Multi-lane receiver de-skewing May 30, 2006
A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal ou
7003059 Jabber counter mechanism for elastic buffer operation February 21, 2006
An Elastic Buffer is provided to process data in a computer network and a write controller is provided to control memory storage operation of such an Elastic Buffer. The write controller may comprise a comparator mechanism which detects if link data from a source contains an IDLE sig
6842840 Controller which determines presence of memory in a node of a data network January 11, 2005
A system for determining whether a memory is connected to a controller in a node of a data network. In order to utilize non-volatile memory elsewhere in the system, it is possible to eliminate the EEPROM which is normally connected to the controller. In order to indicate that the EEPROM
6775719 Host-fabric adapter and method of connecting a host system to a channel-based switched fabric in August 10, 2004
A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged to interface a host memory of the host system; a serial interface arranged to receive and
6751235 Communication link synchronization method June 15, 2004
A communication link is synchronized by a network interface having a transmitter in a core clock domain different from the link clock domain of the communication link. A link synchronization state machine controls the link synchronization process. The functionality of the link synchr
6747997 Network channel receiver architecture June 8, 2004
A network interface controller connects a processing system to receive data from a network fabric through a serial link. The data on the link is clocked in a link clock domain that is different than the core clock domain of the network interface controller. A physical interface operates
6745353 Method and apparatus for sliding window link physical error detection June 1, 2004
Method and apparatus for link physical error tracking that includes a one or more shift registers, one or more counters, and a comparator. The shift register receives one or more status bits for an input data stream denoting whether bytes of the input data stream have a link physical
6741602 Work queue alias system and method allowing fabric management packets on all ports of a cluster May 25, 2004
A device, method and computer program to receive and identify incoming cell data transmitted to a cluster adapter as a request for acknowledgment from a fabric manager server so that the fabric manager server may configure a computer network. This device, method and computer allows for d
6671837 Device and method to test on-chip memory in a production environment December 30, 2003
A device and method to test memory embedded in a chip in which the memory is not directly accessible from a tester external to the chip. The device and method uses a state machine embedded in control circuitry of the chip to execute software to test the memory embedded on the chip. The s
6625768 Test bus architecture September 23, 2003
A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select sign
6587996 Device and method for increased fault coverage using scan insertion techniques around synchronou July 1, 2003
A device and method to test a circuit in a chip that has memory embedded in the chip using a scan chain. This device and method generates a known signal simultaneously to a bypass circuit and the memory onboard the chip. The bypass circuit uses a series of exclusive OR gates, a flip-flop
6298006 Method and apparatus to automatically determine the size of an external EEPROM October 2, 2001
The present invention automatically determines the size of an EEPROM in a circuit. A controller is connected to the EEPROM with both a "data to" the EEPROM connection and a "data from" the EEPROM connection. The controller begins to send logical low address bits over the "data to" the EE

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