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Inventor: Renno; Erik K.
Address: Trondheim, NO
No. of patents: 3
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 7555514 |
Packed add-subtract operation in a microprocessor |
June 30, 2009 |
| A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation |
| 7478224 |
Microprocessor access of operand stack as a register file using native instructions |
January 13, 2009 |
| A combined native (RISC or CISC) microprocessor and stack (Java.TM.) machine are constructed so that Java.TM. VM instructions can be executed in hardware. Most Java.TM. instructions are executed directly, while more complex Java.TM. instructions, such as those manipulating Java.TM. o |
| 7243210 |
Extracted-index addressing of byte-addressable memories |
July 10, 2007 |
| A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A |
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