Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Reif; James R.
Address:
Houston, TX
No. of patents:
10
Patents:












Patent Number Title Of Patent Date Issued
7028106 Remapping routing information entries in an expander April 11, 2006
A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of the interfaces, w
6961813 System and method for providing multi-initiator capability to an ATA drive November 1, 2005
A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is impl
6948036 System and method for providing multi-initiator capability to an ATA drive September 20, 2005
A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is impl
6357013 Circuit for setting computer system bus signals to predetermined states in low power mode March 12, 2002
A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a
6243817 Device and method for dynamically reducing power consumption within input buffers of a bus inter June 5, 2001
A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of input buffers which can be selectively connected and disconnected in a dynamic fashion according to active and inactive signals
6230227 Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridg May 8, 2001
A computer system for supporting a subtractive agent on a secondary PCI bus is provided. A bridge resides between a primary PCI bus and a secondary PCI bus. Where both a master device and a target device reside on the secondary PCI bus, the bridge employs one of two protocols to permit
5867728 Preventing corruption in a multiple processor computer system during a peripheral device configu February 2, 1999
To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configurat
5796992 Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mo August 18, 1998
A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a
5740454 Circuit for setting computer system bus signals to predetermined states in low power mode April 14, 1998
A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STAND BY mode. The computer system includes a PCI bus and an ISA bus, with a
5721935 Apparatus and method for entering low power mode in a computer system February 24, 1998
A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a










 
 
  Recently Added Patents
Quaternary chalcogenide wafers
Method to trace video content processed by a decoder
Semiconductor light-receiving device
Rechargeable battery
Use of natriuretic peptide for treating heart failure
Resist composition and method for producing resist pattern
Non-transitory computer readable recording medium storing print management program, print management device, print management method, and print system
  Randomly Featured Patents
IC test software system for mapping logical functional test data of logic integrated circuits to physical representation
High speed electrical connector having improved housing
Effervescing or foaming bath shape or solid
Belt filter press and belt for same
ESD protection for pass-transistors in a voltage regulator
Nanoparticle filtration
Swivel threaded end male sewer fitting
Sulfur and copper-containing lubricant compositions
Video conferencing system, conference terminal and image server
Applicator for coloring antiseptic