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Inventor:
Reed; David G.
Address:
Saratoga, CA
No. of patents:
27
Patents:












Patent Number Title Of Patent Date Issued
8284620 Memory controller-adaptive 1T/2T timing control October 9, 2012
Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address
8120614 Screen compression for mobile applications February 21, 2012
One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the scr
8098254 Power savings in a computing device during video playback January 17, 2012
Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to r
8069355 Data path controller with integrated power management to manage power consumption of a computing November 29, 2011
A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data
7925907 Using non-lossless compression to save power April 12, 2011
Circuits, methods, and systems that reduce or eliminate the number of data transfers between a system memory and a graphics processor under certain conditions. After inactivity by a user of an electronic device is detected, the color fidelity of pixels being displayed is reduced. Color
7920701 System and method for digital content protection April 5, 2011
A digital content system is disclosed. A security engine disposed in a bridge provides cryptographic services. Clear text digital data received from a central processing unit is encrypted and transferred via the bridge over unsecured data paths as cipher text.
7882296 Deadlock avoidance in a bus fabric February 1, 2011
Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on
7876327 Power savings in a computing device during video playback January 25, 2011
Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to r
7849342 Method and system for implementing generalized system stutter December 7, 2010
A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power stat
7813204 Method and system for memory thermal load sharing using memory on die termination October 12, 2010
Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory com
7746349 Method and apparatus for display of data June 29, 2010
To display a row of characters in the VGA alphanumeric mode, the ASCII and attribute bits for all such characters are retrieved from the main memory and stored in a local cache memory. The font and unused bits that are also retrieved from the memory during the retrieval of ASCII and
7688325 Screen compression for mobile applications March 30, 2010
One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen.
7584321 Memory address and datapath multiplexing September 1, 2009
Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a sing
7571296 Memory controller-adaptive 1T/2T timing control August 4, 2009
Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address
7546483 Offloading RAID functions to a graphics coprocessor June 9, 2009
Systems and methods for using a graphics processor to perform RAID parity functions may improve disk access performance. A method is provided for configuring a graphics processor to perform XOR parity computations when data is written to the RAID array. Another method is provided for
7495985 Method and system for memory thermal load sharing using memory on die termination February 24, 2009
Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory com
7487371 Data path controller with integrated power management to manage power consumption of a computing February 3, 2009
A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data
7478189 Deadlock avoidance in a bus fabric January 13, 2009
Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on
7418537 Deadlock avoidance in a bus fabric August 26, 2008
Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on
7315912 Deadlock avoidance in a bus fabric January 1, 2008
Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on
7289125 Graphics device clustering with PCI-express October 30, 2007
A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminati
7287145 System, apparatus and method for reclaiming memory holes in memory composed of identically-sized October 23, 2007
A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are otherwise unusabl
7275143 System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel September 25, 2007
A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those accesses. In one embod
7240179 System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized July 3, 2007
A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system
7191088 Method and system for memory temperature detection and thermal load management March 13, 2007
A method and system for memory temperature measurement. The method includes the step of monitoring a plurality of accesses to a memory component. A number of accesses occurring to the memory component over a time period is determined. A temperature of the memory component is determin
7081896 Memory request timing randomizer July 25, 2006
Methods and apparatus for changing the timing of memory requests in a graphics system. Reading data from memory in a graphics system causes ground bounce and other electrical noise. The resulting ground bounce may be undesirably synchronized with a video retrace signal sent to a disp
7054987 Apparatus, system, and method for avoiding data writes that stall transactions in a bus interfac May 30, 2006
A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transaction request would fi










 
 
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