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Redman-White; William
Hampshire, GB
No. of patents:

Patent Number Title Of Patent Date Issued
8283955 Double data rate interface October 9, 2012
The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the
6208173 Peak detector March 27, 2001
A peak detector comprises a device for storing a value representing the currently detected peak amplitude (C.sub.p,C.sub.n), a circuit for detecting whether the input signal amplitude exceeds the stored value (D1 to D4), an apparatus for updating the stored value at a fast rate if the

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