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Inventor:
Reddy; Vijay Kumar
Address:
Plano, TX
No. of patents:
4
Patents:




Patent Number Title Of Patent Date Issued
7385383 Methods and systems for determining efficacy of stress protection circuitry June 10, 2008
Methods and systems are provided for determining efficacy of stress protection circuitry. The methods and systems employ a ring oscillator that models at least one parameter of a functional circuit to be protected by the stress protection circuit. A stress signal is applied to the ri
7196887 PMOS electrostatic discharge (ESD) protection device March 27, 2007
A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, an
7026838 Versatile system for accelerated stress characterization of semiconductor device structures April 11, 2006
The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each
6933731 Method and system for determining transistor degradation mechanisms August 23, 2005
According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay elements. Each delay element operates as a delay element through the use of one or more transistors of only a first type and no trans


 
 
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