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Rawlinson; Stephen J.
Sunnyvale, CA
No. of patents:

Patent Number Title Of Patent Date Issued
5490255 Expedited execution of pipelined command having self-ordering operand processing requirements February 6, 1996
A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack queue and presented to the X stag
5426783 System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/39 June 20, 1995
A processing system comprising a first means for generating first signals indicating when the next instruction can begin processing where eight or less bytes are processed by the MOVE, PACK or UNPACK instruction, a second means for generating second signals if an overlap condition exists
4817048 Divider with quotient digit prediction March 28, 1989
A divider, which performs division in a base other than 2, that reduces in most cases the number of cycles it takes to generate each quotient digit. This involves predicting the minimum possible quotient digit in response to leading digits of the partial remainder and of the divisor. The
4802088 Method and apparatus for performing a pseudo branch in a microword controlled computer system January 31, 1989
A microword controlled computer system with an apparatus for performing a pseudo branch. The pseudo branch involves the re-execution of a selected microword in a microword register. The computer system comprises a microword register, N control stores, an apparatus for selectively tra
4800516 High speed floating-point unit January 24, 1989
In a floating point arithmetic unit, high speed computation is achieved by providing logic for determining whether operands of an instruction have a predetermined condition with respect to the instruction and logic responsive thereto for bypassing selective primitive operations when such
4792793 Converting numbers between binary and another base December 20, 1988
Dedicated convert hardware is disclosed for performing bidirectional conversions of numbers between binary and another base b (illustratively decimal) for use in a data processing system. The dedicated convert hardware comprises a special purpose multiply-and-add unit and a convert r
4773035 Pipelined data processing system utilizing ideal floating point execution condition detection September 20, 1988
An instruction execution unit receives instructions and, in turn, provides a sequence of control words to specify the sequential processing of the operand data provided with the instruction. A sequencer nominally issues a first sequence of control words corresponding to the instruction.
4761756 Signed multiplier with three port adder and automatic adjustment for signed operands August 2, 1988
Disclosed is a signed multiplier for use in a data processing system that handles 2's complement operands. The signed multiplier operates to form a preliminary product independently of the signs of the multiplier and multiplicand. While the multiplication is in progress, the signs of the
4760550 Saving cycles in floating point division July 26, 1988
In dividing a pair of binary coded, hexidecimal floating point numbers, leading zero quotient bits are eliminated by comparing the magnitudes of the most significant digits of the fractional parts of the dividend and divisor after the dividend and divisor have been normalized.
4707783 Ancillary execution unit for a pipelined data processing system November 17, 1987
An ancillary execution unit is interfaced to a primary execution unit of a data processing system where the ancillary unit operates faster than the primary for certain instructions and allows for bypassing the slower unit. The primary execution unit has an instruction input receiving an
4685058 Two-stage pipelined execution unit and control stores August 4, 1987
A two control store scheme with instruction execution overlay is shown in a data processing system execution unit having a two-state pipeline. The first control store controls the first-stage facilities during the first cycle of instruction execution and points to the initial location of
4578750 Code determination using half-adder based operand comparator March 25, 1986
Disclosed is a method and apparatus for predicting the condition code of a condition-code-setting instruction by comparing operands in a data processing system. An operand comparator includes one or more half-adders to predict carry outs at an early time. The comparator is used in a data

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