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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ramsbey; Mark
Address:
Sunnyvale, CA
No. of patents:
30
Patents:












Patent Number Title Of Patent Date Issued
7507661 Method of forming narrowly spaced flash memory contact openings and lithography masks March 24, 2009
A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first directio
7176113 LDC implant for mirrorbit to improve Vt roll-off and form sharper junction February 13, 2007
The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relat
7163860 Method of formation of gate stack spacer and charge storage materials having reduced hydrogen co January 16, 2007
The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a
7060554 PECVD silicon-rich oxide layer for reduced UV charging June 13, 2006
A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing V.sub.t. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0.
7033957 ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in fla April 25, 2006
Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; trea
6989320 Bitline implant utilizing dual poly January 24, 2006
The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off.
6989319 Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices January 24, 2006
Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to
6958511 Flash memory device and method of fabrication thereof including a bottom oxide layer with two re October 25, 2005
Process of fabricating multi-bit charge trapping dielectric flash memory device, including forming on a semiconductor substrate a bottom oxide layer to define a substrate/oxide interface, in which the bottom oxide layer includes a first oxygen concentration and a first nitrogen conce
6855608 Method of fabricating a planar structure charge trapping memory cell array with rectangular gate February 15, 2005
A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is
6770938 Diode fabrication for ESD/EOS protection August 3, 2004
An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply V.sub.CC and a second power supply V.sub.SS. An input protection device is also provided which is
6680509 Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONO January 20, 2004
A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterne
6579778 Source bus formation for a flash memory using silicide June 17, 2003
A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating ga
6486029 Integration of an ion implant hard mask structure into a process for fabricating high density me November 26, 2002
A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the
6444530 Process for fabricating an integrated circuit with a self-aligned contact September 3, 2002
A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gat
6440797 Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SO August 27, 2002
A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned
6436766 Process for fabricating high density memory cells using a polysilicon hard mask August 20, 2002
A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The proce
6433383 Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor devi August 13, 2002
A single interpoly dielectric layer is provided for use in semiconductor devices. The single interpoly dielectric layer being formed of silicon graded such that certain regions within the single interpoly dielectric layer are either oxygen-rich or nitrogen-rich. The single interpoly
6410443 Method for removing semiconductor ARC using ARC CMP buffing June 25, 2002
The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemi
6403420 Nitrogen implant after bit-line formation for ONO flash memory devices June 11, 2002
A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of s
6399446 Process for fabricating high density memory cells using a metallic hard mask June 4, 2002
A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The
6395654 Method of forming ONO flash memory devices using rapid thermal oxidation May 28, 2002
A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of s
6362051 Method of forming ONO flash memory devices using low energy nitrogen implantation March 26, 2002
A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of s
6274433 Methods and arrangements for forming a floating gate in non-volatile memory semiconductor device August 14, 2001
Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space
6252276 Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide June 26, 2001
Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the
6251717 Viable memory cell formed using rapid thermal annealing June 26, 2001
A method for forming viable floating gate memory cells in a semiconductor substrate. At various points within the memory cell manufacturing process rapid thermal annealing is used to repair any damage that may be caused to the crystals in the substrate by various processing steps. By qui
6117730 Integrated method by using high temperature oxide for top oxide and periphery gate oxide September 12, 2000
A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silico
6034394 Methods and arrangements for forming a floating gate in non-volatile memory semiconductor device March 7, 2000
Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space
5972751 Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semicond October 26, 1999
Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the
5907781 Process for fabricating an integrated circuit with a self-aligned contact May 25, 1999
A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gat
5869385 Selectively oxidized field oxide region February 9, 1999
A field oxide region is formed with a reduced bird's beak by selectively implanting impurity atoms into the semiconductor substrate to increase the oxidation rate of the substrate and thermally oxidizing the implanted region of the semiconductor substrate. In another embodiment, a gate o










 
 
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