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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ramesh; T. R.
Address:
Newark, CA
No. of patents:
6
Patents:












Patent Number Title Of Patent Date Issued
7069421 Side tables annotating an instruction stream June 27, 2006
A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by
7013456 Profiling execution of computer programs March 14, 2006
A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially conc
6941545 Profiling of computer programs executing in virtual memory systems September 6, 2005
A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's phy
6826748 Profiling program execution into registers of a computer November 30, 2004
A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the
6701426 Switching between a plurality of branch prediction processes based on which instruction set is o March 2, 2004
A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which
6578134 Multi-branch resolution June 10, 2003
A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which










 
 
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