| Patent Number |
Title Of Patent |
Date Issued |
| 6219773 |
System and method of retiring misaligned write operands from a write buffer |
April 17, 2001 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5963984 |
Address translation unit employing programmable page size |
October 5, 1999 |
| Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside buffers. Selective comparisons between contents on a linear address bus and linear address tags a |
| 5907860 |
System and method of retiring store data from a write buffer |
May 25, 1999 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5835949 |
Method of identifying and self-modifying code |
November 10, 1998 |
| A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction |
| 5752274 |
Address translation unit employing a victim TLB |
May 12, 1998 |
| An address translation unit is disclosed employing a direct-mapped translation lookaside buffer and a relatively small, associative victim translation lookaside buffer for translating linear addresses to physical addresses expediently and avoiding thrashing, without requiring large a |
| 5740398 |
Program order sequencing of data in a microprocessor with write buffer |
April 14, 1998 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5615402 |
Unified write buffer having information identifying whether the address belongs to a first write |
March 25, 1997 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5596740 |
Interleaved memory conflict resolution with accesses of variable bank widths and partial return |
January 21, 1997 |
| A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A first and a second port make data read, data write, and instruction fetch requests to/from the |
| 5584009 |
System and method of retiring store data from a write buffer |
December 10, 1996 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5471598 |
Data dependency detection and handling in a microprocessor with write buffer |
November 28, 1995 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5291498 |
Error detecting method and apparatus for computer memory having multi-bit output memory circuits |
March 1, 1994 |
| An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single b |
