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Purayath; Vinod R.
Santa Clara, CA
No. of patents:

Patent Number Title Of Patent Date Issued
8575000 Copper interconnects separated by air gaps and method of making thereof November 5, 2013
A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps i
8105867 Self-aligned three-dimensional non-volatile memory fabrication January 31, 2012
A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching
7919809 Dielectric layer above floating gate for reducing leakage current April 5, 2011
A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage
7915664 Non-volatile memory with sidewall channels and raised source/drain regions March 29, 2011
A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the s
7915124 Method of forming dielectric layer above floating gate for reducing leakage current March 29, 2011
A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed

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