| Patent Number |
Title Of Patent |
Date Issued |
| 7498882 |
Signaling system with low-power automatic gain control |
March 3, 2009 |
| An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within th |
| 7495513 |
Signaling system with low-power automatic gain control |
February 24, 2009 |
| An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within th |
| 7460565 |
Data communications circuit with multi-stage multiplexing |
December 2, 2008 |
| In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely |
| 7414489 |
Phase controlled oscillator circuit with input signal coupler |
August 19, 2008 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 7319345 |
Wide-range multi-phase clock generator |
January 15, 2008 |
| A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plu |
| 7268706 |
Low power, DC-balanced serial link transmitter |
September 11, 2007 |
| A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of |
| 7199728 |
Communication system with low power, DC-balanced serial link |
April 3, 2007 |
| A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords repr |
| 7187721 |
Transition-time control in a high-speed data transmitter |
March 6, 2007 |
| Transition time of a data signal is controlled by applying different delays to the data signal and combining the delayed data signals. The transition time of the data output is determined by difference in delays applied to the data input and may be proportional to bit time of the bit |
| 7135925 |
Adaptive bias scheme for high-voltage compliance in serial links |
November 14, 2006 |
| A high-speed serial-link driver transmits a differential data signal to a conventional differential receiver via a differential channel. The driver employs termination voltages that are high, relative to the supply voltage employed by the transmitter core logic, to support communication |
| 7088270 |
Low power, DC-balanced serial link |
August 8, 2006 |
| A receiver for a data communication system which comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a |
| 7078979 |
Phase controlled oscillator circuit with input signal coupler |
July 18, 2006 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 7061406 |
Low power, DC-balanced serial link transmitter |
June 13, 2006 |
| A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of |
| 6952431 |
Clock multiplying delay-locked loop for data communications |
October 4, 2005 |
| In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provides a multiplied c |
| 6937073 |
Frequency multiplier with phase comparator |
August 30, 2005 |
| A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control th |
| 6861916 |
Phase controlled oscillator circuit with input signal coupler |
March 1, 2005 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 6807186 |
Architectures for a single-stage grooming switch |
October 19, 2004 |
| A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslo |
| 6674772 |
Data communications circuit with multi-stage multiplexing |
January 6, 2004 |
| In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely |
| 6617936 |
Phase controlled oscillator |
September 9, 2003 |
| An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in |
| 6556628 |
Methods and systems for transmitting and receiving differential signals over a plurality of cond |
April 29, 2003 |
| Methods and systems for differential signaling include transmitting differential signals over N conductors, where N is greater than 2, from a sender to a receiver. The sender includes multiple transmitters that receive digital data and produce output signals based on the digital data. |
| 6476656 |
Low-power low-jitter variable delay timing circuit |
November 5, 2002 |
| The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay element supply line |
| 6316987 |
Low-power low-jitter variable delay timing circuit |
November 13, 2001 |
| The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay clement supply line |
| 6275072 |
Combined phase comparator and charge pump circuit |
August 14, 2001 |
| A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control th |
| 5481669 |
Architecture and apparatus for image generation utilizing enhanced memory devices |
January 2, 1996 |
| A system for image generation comprising a plurality of renderers, each having a geometry processor and a rasterizer, that operate in parallel to compute pixel values for a set of primitive objects that comprise the image to be rendered. The geometry processor transforms graphics primiti |
| 5388206 |
Architecture and apparatus for image generation |
February 7, 1995 |
| A system for image generation comprising a plurality of renderers, each having a geometry processor and a rasterizer, that operate in parallel to compute pixel values for a set of primitive objects that comprise the image to be rendered. The geometry processor transforms graphics primiti |
