| Patent Number |
Title Of Patent |
Date Issued |
| 7577830 |
Peripheral device with hardware linked list |
August 18, 2009 |
| A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral includes the hardware linked list to provide a list of capabilities to a querying device. The |
| 7318146 |
Peripheral device with hardware linked list |
January 8, 2008 |
| A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral includes the hardware linked list to provide a list of capabilities to a querying device. The |
| 6993612 |
Arbitration method for a source strobed bus |
January 31, 2006 |
| A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard bu |
| 6983406 |
Method and system for partial-scan testing of integrated circuits |
January 3, 2006 |
| A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit. The failed functional block is then logically isolated from the remaining non-failing fu |
| 6961799 |
Method of detecting a source strobe event using change detection |
November 1, 2005 |
| A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The link bus protocol establishes a method in which data receiving |
| 6948106 |
Method and system for partial-scan testing of integrated circuits |
September 20, 2005 |
| A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit. The failed functional block is then logically isolated from the remaining non-failing fu |
| 6910093 |
Method of pacing and disconnecting transfers on a source strobed bus |
June 21, 2005 |
| A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard bu |
| 6901475 |
Link bus for a hub based computer architecture |
May 31, 2005 |
| A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard bu |
| 6901466 |
Apparatus for extending the available number of configuration registers |
May 31, 2005 |
| A method for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent functions are used for other purposes. Memory is configured to allow enumeration software to conclude that the non-existent function |
| 6836875 |
Method for inserting repeater cells in a deep sub-micron design |
December 28, 2004 |
| A method is provided in which repeater cells are automatically inserted within a sub-micron design before the physical design of the die has been started. The method automatically inserts a predetermined number of repeater cells within the interconnect lines that couple functional blocks |
| 6654918 |
Method and system for partial-scan testing of integrated circuits |
November 25, 2003 |
| A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit. The failed functional block is then logically isolated from the remaining non-failing fu |
| 6651122 |
Method of detecting a source strobe event using change detection |
November 18, 2003 |
| A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The link bus protocol establishes a method in which data receiving |
| 6593932 |
System for implementing a graphic address remapping table as a virtual register file in system m |
July 15, 2003 |
| A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data using an indirect addressing scheme t |
| 6588001 |
Method for inserting repeater cells in a deep sub-micron design |
July 1, 2003 |
| A method is provided in which repeater cells are automatically inserted within a sub-micron design before the physical design of the die has been started. The method automatically inserts a predetermined number of repeater cells within the interconnect lines that couple functional blocks |
| 6587868 |
Computer system having peer-to-peer bus bridges and shadow configuration registers |
July 1, 2003 |
| A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the |
| 6542953 |
Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration |
April 1, 2003 |
| A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the |
| 6515483 |
System for partial scan testing of integrated circuits |
February 4, 2003 |
| A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit. The failed functional block is then logically isolated from the remaining non-failing fu |
| 6480974 |
Method for use of bus parking states to communicate diagnostic information |
November 12, 2002 |
| A system for flexibly and efficiently communicating diagnostic information about an integrated ASIC device. Where the ASIC is associated with a PCI bus, the bus parking or idle state for the PCI bus is used for placing status or diagnostic information relating to or about the ASIC on the |
| 6480951 |
System for issuing device requests by proxy |
November 12, 2002 |
| A system for issuing device requests by proxy in a system using distributed control through a multi-port switch. A device issues a request to a central switch indicating the original requester as the source rather than itself. This passes responsibility for the control of the actual data |
| 6418523 |
Apparatus comprising a translation lookaside buffer for graphics address remapping of virtual ad |
July 9, 2002 |
| A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, |
| 6360289 |
System for autonomous configuration of peer devices |
March 19, 2002 |
| A system for autonomously configuring peer devices without unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, the compatibility bridge monitors the status of the configuration cycle on the host bus. The compatibility bridge determines |
| 6349347 |
Method and system for shortening boot-up time based on absence or presence of devices in a compu |
February 19, 2002 |
| A method of configuring peer devices without the unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices located on the host bus. A watchdog timer times out after a predetermined duration when the |
| 6301645 |
System for issuing device requests by proxy |
October 9, 2001 |
| A system for issuing device requests by proxy in a system using distributed control through a multi-port switch. A device issues a request to a central switch indicating the original requester as the source rather than itself. This passes responsibility for the control of the actual data |
| 6282625 |
GART and PTES defined by configuration registers |
August 28, 2001 |
| A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, |
| 6282589 |
System for sharing data buffers from a buffer pool |
August 28, 2001 |
| A buffer pool is described for buffering data transfers between components within a computer system. The buffer pool uses a translation table to translate virtual address pointers from calling computer components into physical address pointers within a line buffer array. The virtual addr |
| 6275888 |
Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration |
August 14, 2001 |
| A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the |
| 6272576 |
Method for extending the available number of configuration registers |
August 7, 2001 |
| A method for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent functions are used for other purposes. Memory is configured to allow enumeration software to conclude that the non-existent function |
| 6266770 |
Method for autonomous configuration of peer devices |
July 24, 2001 |
| A method of autonomously configuring peer devices without unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, the compatibility bridge monitors the status of the configuration cycle on the host bus. The compatibility bridge determines |
| 6249853 |
GART and PTES defined by configuration registers |
June 19, 2001 |
| A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, |
| 6243775 |
System for extending the available number of configuration registers |
June 5, 2001 |
| A system for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent functions are used for other purposes. Memory is configured to allow enumeration software to conclude that the non-existent function |
| 6233638 |
System for configuring peer devices |
May 15, 2001 |
| A system for configuring peer devices without unnecessary delay in boot up time by using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices located on the host bus. A watchdog timer times out after a predetermined duration when the |
| 6195734 |
System for implementing a graphic address remapping table as a virtual register file in system m |
February 27, 2001 |
| A system for implementing a graphics address remapping table as a virtual register in system memory. The remapping table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data using an indirect addressing scheme th |
| 6192457 |
Method for implementing a graphic address remapping table as a virtual register file in system m |
February 20, 2001 |
| A method for implementing a graphics address remapping table as a virtual register in system memory. The remapping table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data. The method uses an indirect addressin |
| 6161153 |
Method for sharing data buffers from a buffer pool |
December 12, 2000 |
| A method is described for buffering data transfers between components within a computer system. The method uses a buffer pool and translation table to translate virtual address pointers from calling computer components into physical address pointers within a line buffer array. The vi |
| 6145040 |
Method and system for apportioning computer bus bandwidth |
November 7, 2000 |
| A method and system interfaces a plurality of bus requesters with a computer bus having a bus bandwidth. The bus bandwidth is apportioned among the plurality of bus requesters by assigning to a selected bus requester a portion of the bus bandwidth based on how much the selected bus r |
| 6141715 |
Method and system for avoiding live lock conditions on a computer bus by insuring that the first |
October 31, 2000 |
| A computer system avoids livelock conditions on a computer bus coupled to plural bus masters. In response to receiving a transaction request from a first bus master across the computer bus, a bus controller transmits a retry command to the first bus master if the bus controller is unable |
| 6122677 |
Method of shortening boot uptime in a computer system |
September 19, 2000 |
| A method of configuring peer devices without the unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices located on the host bus. A watchdog timer times out after a predetermined duration when the |
| 6112316 |
System for use of bus parking states to communicate diagnostic information |
August 29, 2000 |
| A system for flexibly and efficiently communicating diagnostic information about an integrated ASIC device. Where the ASIC is associated with a PCI bus, the bus parking or idle state for the PCI bus is used for placing status or diagnostic information relating to or about the ASIC on the |
| 6108733 |
Method for extending the available number of configuration registers |
August 22, 2000 |
| A method for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent functions are used for other purposes. Memory is configured to allow enumeration software to conclude that the non-existent function |
| 6092219 |
Method for use of bus parking states to communicate diagnostic information |
July 18, 2000 |
| A system for flexibly and efficiently communicating diagnostic information about an integrated ASIC device. Where the ASIC is associated with a PCI bus, the bus parking or idle state for the PCI bus is used for placing status or diagnostic information relating to or about the ASIC on the |
| 6069638 |
System for accelerated graphics port address remapping interface to main memory |
May 30, 2000 |
| A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, |
| 6067581 |
Method for identifying the orignal source device in a transaction request initiated from address |
May 23, 2000 |
| A method for issuing device requests by proxy in a system using distributed control through a multi-port switch. A device issues a request to a central switch indicating the original requester as the source rather than itself. This passes responsibility for the control of the actual data |
| 5991843 |
Method and system for concurrent computer transaction processing |
November 23, 1999 |
| A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first |
| 5978872 |
Method and system for concurrent computer transaction processing |
November 2, 1999 |
| A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first |
| 5920881 |
Method and system for using a virtual register file in system memory |
July 6, 1999 |
| A computer bridge processes transactions in a computer system that includes a system memory. The bridge includes a first address decoder that allocates address space to the system memory according to a first allocation scheme and, in response to receiving transaction requests, direct |
| 5878235 |
Method and system for concurrent computer transaction processing |
March 2, 1999 |
| A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first |
| 5740380 |
Method and system for apportioning computer bus bandwidth |
April 14, 1998 |
| A method and system interfaces a plurality of bus requesters with a computer bus having a bus bandwidth. The bus bandwidth is apportioned among the plurality of bus requesters by assigning to a selected bus requester a portion of the bus bandwidth based on how much the selected bus r |
| 5430742 |
Memory controller with ECC and data streaming control |
July 4, 1995 |
| Data is written to a memory subsystem in a computer system, wherein the data is supplied by an input/output (I/O) bus. The I/O bus provides a STROBE signal, the occurrence of which is indicative of a time when an I/O data word on the I/O bus is valid. A first I/O data word provided by th |
