A parallel carry and carry propagation generator for use with a modulo-2 N-bit operand adder generates the required carry bits to complete the N-bit pair modulo-2 sums as a parallel operation. The logic structure has log.sub.2 2N operation levels that allow for constant fan-in and fan-ou
A floating point number which includes a mantissa field, an exponent field, and a sign field is converted to an integer of n-bit size including a sign bit. The sign field is examined to determine if the floating point number is a positive or negative number. The mantissa field is shifted
Multistage leading zero detection is used in a left-shift normalization unit for normalizing floating-point mantissas. Detection of the leading one is accomplished by segmenting the mantissa into non-overlapping segments. The most significant segment containing a non-zero value bit is
