| Patent Number |
Title Of Patent |
Date Issued |
| 7521973 |
Clock-skew tuning apparatus and method |
April 21, 2009 |
| A method for detecting which of two clock signals is the first to arrive may include providing a sense amplifier comprising first and second nodes located on first and second legs thereof. The sense amplifier is configured such that the first and second nodes have a substantially equ |
| 7489204 |
Method and structure for chip-level testing of wire delay independent of silicon delay |
February 10, 2009 |
| Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selectively connected to ei |
| 7487487 |
Design structure for monitoring cross chip delay variation on a semiconductor device |
February 3, 2009 |
| A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a "schmoo plot" by varying a frequency |
| 7444608 |
Method and system for evaluating timing in an integrated circuit |
October 28, 2008 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
| 7418689 |
Method of generating wiring routes with matching delay in the presence of process variation |
August 26, 2008 |
| A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a seco |
| 7401307 |
Slack sensitivity to parameter variation based timing analysis |
July 15, 2008 |
| A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on eac |
| 7302673 |
Method and system for performing shapes correction of a multi-cell reticle photomask design |
November 27, 2007 |
| A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for |
| 7290191 |
Functional frequency testing of integrated circuits |
October 30, 2007 |
| A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits b |
| 7280939 |
System and method of analyzing timing effects of spatial distribution in circuits |
October 9, 2007 |
| Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of i |
| 7089143 |
Method and system for evaluating timing in an integrated circuit |
August 8, 2006 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
