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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Poisner; David I.
Address:
Folsom, CA
No. of patents:
63
Patents:


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Patent Number Title Of Patent Date Issued
7941860 Apparatus and method for content protection using one-way buffers May 10, 2011
Method and apparatus for content protection using one-way buffers. In one embodiment, the method includes storage of content decrypted by a host processor within a reserved range of memory. In one embodiment, a peripheral device requires the host processor to decrypt the received con
7921293 Apparatus and method for unilaterally loading a secure operating system within a multiprocessor April 5, 2011
An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memo
7903502 Automatic read of current time when exiting low-power state utility March 8, 2011
A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register and a calculation
7817769 Real time clock rate checker and recovery mechanism October 19, 2010
A circuit, method, and system are disclosed. In one embodiment the circuit comprises a ring oscillator circuit having a plurality of delay elements, the ring oscillator circuit to generate a clock signal frequency, a checker circuit to compare a count of clock signal oscillations observe
7797728 Mechanism to generate restricted and unrestricted execution environments September 14, 2010
According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU) having a first thread having first associated thread identification (ID) and a second thread having second associated thread ID. The computer system also includes a
7783809 Virtualization of pin functionality in a point-to-point interface August 24, 2010
Architectures and techniques that allow legacy pin functionality to be replaced with a "virtual wire" that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtua
7400554 Automatic read of current time when exiting low-power state July 15, 2008
A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register and a calculation
7398383 Method and system for using internal FIFO RAM to improve system boot times July 8, 2008
Embodiments of methods and systems for improving boot-up time in computer systems utilize RAM in devices separate from the main memory, normally dedicated to another function, to provide a stack and temporary storage during BIOS execution, enabling BIOS to call subroutines and execute in
7392415 Sleep protection June 24, 2008
Methods, apparatus and machine-readable medium are described that attempt to protect secrets from sleep attacks. In some embodiments, the secrets are encrypted and a security enhanced environment dismantled prior to entering a sleep state. Some embodiments further re-establish a security
7366849 Protected configuration space in a protected environment April 29, 2008
A protected configuration space is implemented as at least one range of memory addresses that are mapped to logic external to system memory. The memory addresses access logic that performs control and status operations pertaining to a protected operating environment. Some of the addresse
7363523 Method and apparatus for controlling power management state transitions April 22, 2008
An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage,
7149909 Power management for an integrated graphics device December 12, 2006
In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a g
7130992 Detecting insertion of removable media October 31, 2006
The present invention is a method and system to automatic loading program on a medium into memory for execution. In one embodiment, a mode word is configured. The insertion of the medium into a drive is detected based on the mode word. A program on the medium is started when insertion is
7093115 Method and apparatus for detecting an interruption in memory initialization August 15, 2006
Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit
7076802 Trusted system clock July 11, 2006
Methods, apparatus and computer readable medium are described that attempt increase trust in a system time provided by a system clock. In some embodiments, a detector detects activities that may be associated with attacks against the system clock. Based upon whether the detector detects
7076669 Method and apparatus for communicating securely with a token July 11, 2006
A method and apparatus to communicate with a token using a previously reserved binary number in the start field of a cycle, wherein the cycle is not echoed on any bus other than the bus through which the communication is received.
7076578 Race free data transfer algorithm using hardware based polling July 11, 2006
A method and apparatus for a race free data transfer algorithm using hardware based polling. One disclosed method transfers information between a target device and a buffer which is one of a set of buffers. The buffer is pointed to by a current buffer value stored in a controller. Th
7069367 Method and apparatus for avoiding race condition with edge-triggered interrupts June 27, 2006
An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an edge-triggered interrupt. A power management device receives the interrupt pending signal. If the
7051137 Event delivery May 23, 2006
Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire messag
7024555 Apparatus and method for unilaterally loading a secure operating system within a multiprocessor April 4, 2006
An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory
7017062 Method and apparatus for recovering from an overheated microprocessor March 21, 2006
One embodiment of a system for recovering from an overheated processor includes a processor that asserts a thermal trip signal when the internal temperature of the processor exceeds a maximum acceptable limit. A power management device asserts a power off signal to a voltage regulator
7000056 Method and apparatus for detecting low pin count and serial peripheral interfaces February 14, 2006
Apparatus and method for providing a multiplexed bus supporting the coupling of either one of a device having a first bus type interface and a device having a second bus type interface where the multiplexed bus is made up, at least in part, of a plurality of common signal lines that may
6938153 Method and system for using internal FIFO RAM to improve system boot times August 30, 2005
Embodiments of methods and systems for improving boot-up time in computer systems utilize RAM in devices separate from the main memory, normally dedicated to another function, to provide a stack and temporary storage during BIOS execution, enabling BIOS to call subroutines and execute in
6920553 Method and apparatus for reading initial boot instructions from a bootable device connected to t July 19, 2005
In one embodiment, a design is described for providing the BIOS instructions to a computer through the USB port. At boot-up, a USB controller checks the USB port for a bootable device containing BIOS instructions. If a bootable device is connected, the USB controller transfers the BI
6920535 Accessing multi-ported memory for uncached status and control accesses July 19, 2005
A computer system comprising multi-ported memory electrically coupled to a central processing unit and a peripheral device. The central processing unit and the peripheral device access the multi-ported memory independently.
6911872 Circuit and method for generating a clock signal June 28, 2005
In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a selectable delay circuit. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit prov
6842776 Method for automatic device monitoring by a central computer January 11, 2005
A method for monitoring a plurality of devices in a common environment. The method comprises the steps of receiving usage information from one of the devices and storing the usage information on a memory device of a computer. The method further comprises the steps of using the computer t
6820177 Protected configuration space in a protected environment November 16, 2004
A protected configuration space is implemented as at least one range of memory addresses that are mapped to logic external to system memory. The memory addresses access logic that performs control and status operations pertaining to a protected operating environment. Some of the addresse
6795884 Read-only memory based circuitry for sharing an interrupt between disk drive interfaces September 21, 2004
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no s
6772258 Method and apparatus for sharing an interrupt between disk drive interfaces August 3, 2004
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no s
6772245 Method and apparatus for optimizing data transfer rates between a transmitting agent and a recei August 3, 2004
According to one aspect of the present invention, a method is provided in which a transmitting agent transfers data to a receiving agent at a specified transfer rate. Information relating to data transfer pauses requested by the receiving agent is maintained. The data transfer rate is
6754840 Over-clocking detection system utilizing a reference signal and thereafter preventing over-clock June 22, 2004
An over-clock deterrent mechanism of a chipset which comprises an over-clock detection circuit for detecting over-clocking of a system (processor) clock signal based on comparison of ratio of the system (processor) clock signal which is likely to be over-clocked and a fixed, stable r
6742073 Bus controller technique to control N buses May 25, 2004
A technique for operating a bus controller to control N buses, each bus capable of having at least one device connected thereto, N being an integer greater than 1, includes reading a descriptor inputted to the bus controller and determining from the read descriptor whether a data tra
6742060 Look-up table based circuitry for sharing an interrupt between disk drive interfaces May 25, 2004
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no s
6738848 Decoder-based circuitry for sharing an interrupt between disk drive interfaces May 18, 2004
An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no s
6636912 Method and apparatus for mode selection in a computer system October 21, 2003
According to one embodiment, a computer comprises a central processing unit (CPU), a first hub agent, a first hub interface coupled to the first hub agent, and a second hub agent coupled to the first hub interface. The first and second hub agents operate at a first data clocking rate
6581173 Method and apparatus for verifying that data stored in a memory has not been corrupted June 17, 2003
An integrated circuit device includes dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time.
6567866 Selecting multiple functions using configuration mechanism May 20, 2003
The present invention is a method and apparatus to provide multifunction to a device. A selector selects one of first and second functionalities based on a control setting. The selected one of the first and second functionalities is accessible at a pin of the device. A configuration
6564330 Wakeup circuit for computer system that enables codec controller to generate system interrupt in May 13, 2003
A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their c
6480965 Power management method for a computer system having a hub interface architecture November 12, 2002
According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pend
6438709 Method for recovering from computer system lockup condition August 20, 2002
In one embodiment of a method for recovering from a computer system lockup condition, an interrupt is generated to the computer system's operating system notifying the operating system of the lockup condition. An operating system interrupt handler is then executed. The interrupt handler
6421765 Method and apparatus for selecting functional space in a low pin count memory device July 16, 2002
The present invention is an apparatus and method for selecting one of a first and a second storage element in response to a control signal issued by a processor in a low pin count device. The apparatus comprises a decoder to receive the control signal and an address signal having a s
6374321 Mechanisms for converting address and data signals to interrupt message signals April 16, 2002
In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge including ports to receive an interrupt request signal in the form of address signals and
6269443 Method and apparatus for automatically selecting CPU clock frequency multiplier July 31, 2001
An apparatus for automatically selecting a processor clock frequency multiplier is disclosed. The apparatus includes a reset circuit that transmits a reset signal to a processor. When the reset signal is deasserted, the processor samples the states of various strapping signals that a
6247151 Method and apparatus for verifying that data stored in a memory has not been corrupted June 12, 2001
An integrated circuit device includes dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time.
6178528 Method and apparatus for reporting malfunctioning computer system January 23, 2001
When a computer system malfunction is detected, a malfunction report signal is issued to a communications device that is coupled to a communications network. After the malfunction report signal is issued, the communications device fetches a malfunction report message from a non-volatile
6157970 Direct memory access system using time-multiplexing for transferring address, data, and control December 5, 2000
A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral
6151654 Method and apparatus for encoded DMA acknowledges November 21, 2000
A method and apparatus which may be used for direct memory access (DMA) acknowledges. A method of acknowledging a request for access to a bus from a bus agent access involves receiving a request for access to the bus and generating a request acknowledge signal. The request acknowledge is
6131127 I/O transactions on a low pin count bus October 10, 2000
A system having a bus coupled to a host and a peripheral controller device each coupled to a bus. The bus includes a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device communicates with the host
6119189 Bus master transactions on a low pin count bus September 12, 2000
A system including a host, a peripheral controller device, and a bus master device each coupled to a bus having a plurality of general purpose signal lines for carrying time-multiplexed address, data, and control information. The bus master device communicates with the host and the p
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