| Patent Number |
Title Of Patent |
Date Issued |
| 5796390 |
Redundant shift registers for scanning circuits in liquid crystal display devices |
August 18, 1998 |
| A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly num |
| 5298891 |
Data line defect avoidance structure |
March 29, 1994 |
| A data line defect avoidance structure for a display device having an array of display elements arranged in rows and columns includes a plurality of repair lines overlapping the ends of data lines which extend between the columns. Each repair line spans a set of data lines, and there is |
| 5224102 |
Design and test methodology for redundant shift registers |
June 29, 1993 |
| A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly num |
| 5222082 |
Shift register useful as a select line scanner for liquid crystal display |
June 22, 1993 |
| A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes an output circuit which switches the output terminal between high and low states. A first node switches the output terminal |
| 5170155 |
System for applying brightness signals to a display device and comparator therefore |
December 8, 1992 |
| A system for applying brightness signals to the pixels of a display device includes a transmission gate for each column of pixels. The control electrodes of the transmission gates are precharged to the threshold voltage of the gates to substantially increase the speed of the system. |
| 5136622 |
Shift register, particularly for a liquid crystal display |
August 4, 1992 |
| A shift register includes transistors having conduction paths serially connected at a node and between an input terminal receiving a constant voltage and a clocked terminal receiving a clocked voltage of a first phase. The control electrode of one of the transistors receives a clocked |
| 5113134 |
Integrated test circuit for display devices such as LCD's |
May 12, 1992 |
| A circuit for testing a liquid crystal display for open data lines, for identifying select lines shorted to data lines, and for identifying failed data line scanner stages includes thin film transistors arranged between each data line and a segmented bus. A sectioned shift register s |
| 5105187 |
Shift register for active matrix display devices |
April 14, 1992 |
| A select line scanner circuit for a display device has a plurality of register stages. The register stages each include first and second register segments and first and second latch circuit means which receive select signals and apply oppositely poled logic signals to the output node |
| 4989061 |
Radiation hard memory cell structure with drain shielding |
January 29, 1991 |
| A memory cell structure has a pair of cross-coupled inverters, each inverter having first and second MOS series coupled transistors. Each of the second inverter transistors has a source disposed near the periphery of the cell, a drain disposed closer to the center of the cell than the |
| 4918498 |
Edgeless semiconductor device |
April 17, 1990 |
| A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor material, but the gate electrode does not extend over any sidewall of the silicon island. In order to electrically i |
| 4903094 |
Memory cell structure having radiation hardness |
February 20, 1990 |
| A memory cell structure has a thin insulating oxide barrier layer between an insulating body, such as sapphire, and a conducting layer, such as polysilicon, to prevent photoconduction between the body and the layer. Upper and lower conducting layers form a capacitor with a source and a |
| 4872141 |
Radiation hard memory cell having monocrystalline and non-monocrystalline inverters |
October 3, 1989 |
| A radiation hard memory cell comprises on an insulating substrate a low output impedance inverter made of a monocrystalline semiconductor and a high output impedance inverter made of a non-crystalline semiconductor in order to save space. The semiconductor can be Si and a barrier layer c |
| 4864380 |
Edgeless CMOS device |
September 5, 1989 |
| A common island complementary-metal-oxide semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. Both N-channel and P-Channel transistors are formed in the common island of semiconductor material, but the gate electrode does |
| 4833644 |
Memory cell circuit having radiation hardness |
May 23, 1989 |
| A memory cell circuit has a pair of inverters and a means, such as gate-drain coupled capacitors, for providing a greater voltage difference at MOS transistor gates during radiation than an initial value. This tends to preserve the latch logic state and thus prevent a change in logic sta |
| 4791464 |
Semiconductor device that minimizes the leakage current associated with the parasitic edge trans |
December 13, 1988 |
| A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor island such that the gate electrode extends over the sidewalls of the island. Diodes are formed between the source and |
| 4786955 |
Semiconductor device with source and drain depth extenders and a method of making the same |
November 22, 1988 |
| A semiconductor device having a layer of semiconductor material disposed on an insulating substrate is disclosed. Source and drain depth extenders are provided within the semiconductor material for extending the respective source and drain regions to the insulating substrate. This device |
| 4760557 |
Radiation hard memory cell circuit with high inverter impedance ratio |
July 26, 1988 |
| A memory cell circuit has a pair of cross-coupled inverters. One inverter has an output impedance at least 10 times, preferably, at least 50 times, that of the other inverter so that during a radiation pulse the chance of a change in logic state is reduced. In a particular embodiment, th |
| 4758744 |
Decoder circuitry with reduced number of inverters and bus lines |
July 19, 1988 |
| A decoder circuit for fully decoding N input variables includes 2.sup.N logic gates arranged into 2.sup.N-1 pairs of gates, with each gate having N inputs, and one output. The decoder also includes (N-1) inverters for producing the complements of N-1 of the N input variables whereby the |
