| Patent Number |
Title Of Patent |
Date Issued |
| 7530046 |
Chip debugging using incremental recompilation |
May 5, 2009 |
| While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netl |
| 7467176 |
Saturation and rounding in multiply-accumulate blocks |
December 16, 2008 |
| Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, includin |
| 7437401 |
Multiplier-accumulator block mode splitting |
October 14, 2008 |
| A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operatio |
| 7360196 |
Technology mapping for programming and design of a programmable logic device by equating logic e |
April 15, 2008 |
| A programmable logic device ("PLD") architecture and a user logic design are modeled logically to find an efficient programming solution for the user logic design on the PLD architecture. The logical models are converted to equations--e.g., by representing them as binary decision dia |
| 7337101 |
Method and apparatus for extending the capabilities of tools used for designing systems on progr |
February 26, 2008 |
| A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint. |
| 7290237 |
Method for programming a mask-programmable logic device and device so programmed |
October 30, 2007 |
| A user logic design for a mask-programmable logic device ("MPLD") may be designed on a comparable or compatible user-programmable logic device ("UPLD") and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target |
| 7216330 |
Method and apparatus for extending the capabilities of tools used for designing systems on progr |
May 8, 2007 |
| A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by |
| 7076751 |
Chip debugging using incremental recompilation |
July 11, 2006 |
| While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netl |
| 7058534 |
Method and apparatus for application specific test of PLDs |
June 6, 2006 |
| Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application |
