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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Perego; Richard E.
Address:
San Jose, CA
No. of patents:
59
Patents:


1 2










Patent Number Title Of Patent Date Issued
8214616 Memory controller device having timing offset capability July 3, 2012
A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset s
8165187 Periodic calibration for communication channels by drift tracking April 24, 2012
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure
8144792 Communication channel calibration for drift conditions March 27, 2012
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibrat
7978754 Communication channel calibration with nonvolatile parameter store for recovery July 12, 2011
A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained fr
7965567 Phase adjustment apparatus and method for a memory device signaling system June 21, 2011
Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with
7925808 Memory system and device with serialized data transfer April 12, 2011
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each
7921245 Memory system and device with serialized data transfer April 5, 2011
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each
7848156 Early read after write operation memory device, system and method December 7, 2010
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address
7821519 Scalable unified memory architecture October 26, 2010
A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shar
7668276 Phase adjustment apparatus and method for a memory device signaling system February 23, 2010
Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with
7610447 Upgradable memory system with reconfigurable interconnect October 27, 2009
Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the system is fully populated, there is a one-to-one correspondence between signal line sets an
7577789 Upgradable memory system with reconfigurable interconnect August 18, 2009
Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filt
7523248 System having a controller device, a buffer device and a plurality of memory devices April 21, 2009
A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit
7484064 Method and apparatus for signaling between devices of a memory system January 27, 2009
A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high perform
7478181 Memory system and device with serialized data transfer January 13, 2009
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each
7415073 Communication channel calibration for drift conditions August 19, 2008
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibrat
7400671 Periodic calibration for communication channels by drift tracking July 15, 2008
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure
7400670 Periodic calibration for communication channels by drift tracking July 15, 2008
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure
7398413 Memory device signaling system and method with independent timing calibration for parallel signa July 8, 2008
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comp
7380092 Memory device and system having a variable depth write buffer and preload method May 27, 2008
A variable depth write data buffer is provided in a memory device coupled to a master device by an interconnect structure in an embodiment of the present invention. The variable depth write data buffer reduces a delay, or W-R turnaround bubble, time between a read operation and a write
7369444 Early read after write operation memory device, system and method May 6, 2008
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address
7320047 System having a controller device, a buffer device and a plurality of memory devices January 15, 2008
A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit
7313639 Memory system and device with serialized data transfer December 25, 2007
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each
7237048 Memory system and device with serialized data transfer June 26, 2007
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each
7225311 Method and apparatus for coordinating memory operations among diversely-located memory component May 29, 2007
A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset s
7225292 Memory module with termination component May 29, 2007
A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends
7216187 Memory system including a circuit to convert between parallel and serial bits May 8, 2007
A memory controller comprises a circuit to convert a set of parallel constituent bits to a serial stream of constituent bits. A first output driver receives at least four bits of the serial stream of constituent bits in succession from the circuit. The first output driver outputs the
7210016 Method, system and memory controller utilizing adjustable write data delay settings April 24, 2007
A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared con
7209397 Memory device with clock multiplier circuit April 24, 2007
A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory devi
7206897 Memory module having an integrated circuit buffer device April 17, 2007
A memory module includes an integrated circuit buffer device that receives control information via a connector interface. A first plurality of signal lines carries a first address from the integrated circuit buffer device to a first memory device. A second plurality of signal lines c
7206896 Integrated circuit buffer device April 17, 2007
An integrated circuit buffer device comprises a first receiver circuit to receive control information and address information from a controller device. A first interface includes a first interface portion to provide a first address to a first memory device. A second interface portion
7200710 Buffer device and method of operation in a buffer device April 3, 2007
An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds
7200055 Memory module with termination component April 3, 2007
A memory module having a termination component. The memory module includes first and second memory devices, a termination component and three sets of signal lines. A first set of signal lines is coupled to the first memory device and dedicated to data transfers involving the first memory
7187572 Early read after write operation memory device, system and method March 6, 2007
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment. The memory device includes an interface for providing a first write address, a first write data, and a read address. A memory core is cou
7177998 Method, system and memory controller utilizing adjustable read data delay settings February 13, 2007
A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared con
7170314 Multiple channel modules and bus systems using same January 30, 2007
Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
7095789 Communication channel calibration for drift conditions August 22, 2006
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibrat
7073035 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory m July 4, 2006
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory
7062597 Integrated circuit buffer device June 13, 2006
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through ded
7051151 Integrated circuit buffer device May 23, 2006
An integrated circuit buffer device including a first port and a second port. The first port to receive data from a first integrated circuit memory device, and the second port to receive data from a second integrated circuit memory device. The integrated circuit buffer device further
7043599 Dynamic memory supporting simultaneous refresh and data-access transactions May 9, 2006
Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed
7017002 System featuring a master device, a buffer device and a plurality of integrated circuit memory d March 21, 2006
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through ded
7010642 System featuring a controller device and a memory module that includes an integrated circuit buf March 7, 2006
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through ded
7003618 System featuring memory modules that include an integrated circuit buffer devices February 21, 2006
A computer system includes a controller device having an interface disposed on a circuit board. A first socket is disposed on the circuit board and receives a first memory module having a first integrated circuit buffer device. The first memory module has a first plurality of integra
7000062 System and method featuring a controller device and a memory module that includes an integrated February 14, 2006
A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A first plurality of signal lines are coupled to the first integrated circuit buffer device
6961831 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory m November 1, 2005
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one particular exemplary embodiment, the techniques may be realized through a memory system comprising a memory module and a memory controller. The memory module c
6920540 Timing calibration apparatus and method for a memory device signaling system July 19, 2005
A memory system includes a memory controller and a memory component coupled to each other. An interface of the memory component is configured to receive a first signal from the memory controller with read request information, retrieve the read data information from the memory core in
6898085 Multiple channel modules and bus systems using same May 24, 2005
Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
6889304 Memory device supporting a dynamically configurable core organization May 3, 2005
Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks
6864896 Scalable unified memory architecture March 8, 2005
A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared
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