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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Peng; Chen pin
Address:
Hsinchu Hsien, TW
No. of patents:
8
Patents:












Patent Number Title Of Patent Date Issued
7554599 Image sensor module with air escape hole and a method for manufacturing the same June 30, 2009
An image sensor module with air escape hole includes a substrate having an upper surface and a lower surface. A chip is mounted on the upper surface of the substrate. A plurality of wires are electrically connected the chip to the upper surface of the substrate. An adhered layer is coate
7423334 Image sensor module with a protection layer and a method for manufacturing the same September 9, 2008
An image sensor module with a protection layer and a method for manufacturing the same includes a substrate with an upper surface and a lower surface, a chip is mounted on the upper surface of the substrate, a plurality of wires are electrically connected the bonding pads of the chip
7235869 Integrated circuit package having a resistant layer for stopping flowed glue June 26, 2007
An integrated circuit package comprises a substrate having an upper surface, a lower surface, and a long slot penetrating from the upper surface to the lower surface. The lower surface is formed with a wiring regioins arranged at side of the long slot, and the wiring regions formed w
6642554 Memory module structure November 4, 2003
A memory module structure of the invention is used for being assembled on a locking device. The memory module includes a substrate and a plurality of memories. The substrate has certain long sides and short sides. Notches are formed on the short sides for being secured by the locking dev
6642137 Method for manufacturing a package structure of integrated circuits November 4, 2003
A package structure for an integrated circuit includes a substrate, an integrated circuit, an adhesive layer, a plurality of wirings, and a glue layer. The substrate has a first surface and a second surface. The first surface is formed with a plurality of signal input terminals. The seco
6501187 Semiconductor package structure having central leads and method for packaging the same December 31, 2002
A semiconductor package structure having central leads according to the invention includes a substrate, a semiconductor device, a plurality of wires, and glue. A long slot penetrating through the substrate is formed in the substrate. A plurality of bonding pads formed on the semiconducto
6472736 Stacked structure for memory chips October 29, 2002
A stacked structure for memory chips includes a substrate, a lower memory chip, an upper memory chip, and an insulation medium. The substrate has an upper surface, a lower surface and a slot penetrating through the substrate from the upper surface to the lower surface. The lower memory
6400007 Stacked structure of semiconductor means and method for manufacturing the same June 4, 2002
An stacked structure of semiconductor means and method for manufacturing the same, comprises a substrate, a lower semiconductor chip, an adhered glue layer, a plurality of wires and an upper semiconductor chip. The adhered glue layer located between the substrate and the lower semico










 
 
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