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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Pelley; Perry H.
Address:
Austin, TX
No. of patents:
20
Patents:












Patent Number Title Of Patent Date Issued
8260151 Optical communication integration September 4, 2012
An integrated circuit die has a transistor circuitry section for implementing information handling operations. Optical circuitry is within the single semiconductor die. The optical circuitry includes a laser transmitter and is operably coupled to the transistor circuitry section. The
8169257 System and method for communicating between multiple voltage tiers May 1, 2012
A system includes first, second, and third circuits and first and second capacitors. The first capacitor has a first power supply terminal coupled to positive power supply terminal, a second power supply terminal, and an input/output. The second capacitor has a first power supply termina
8120412 Voltage boosting system with slew rate control and method thereof February 21, 2012
A system includes a voltage controlled oscillator, a charge pump, and a current regulator circuit. The voltage controlled oscillator has a control input and a clock output that provides a clock signal at a clock frequency that is variable. The charge pump is coupled to the clock outp
8014682 Free-space optical communication system September 6, 2011
A free-space communication system and method of operation includes a first communication device physically coupled to a substrate and having an optical transmitter for communicating information. A second communication device is physically coupled to the substrate and has an optical r
8004080 Edge mounted integrated circuits with heat sink August 23, 2011
A module has a substrate, first and second integrated circuits, and a heat sink. The integrated circuits each have a first major surface, a second major surface, a first edge, a second edge, and a third edge and have optical circuits having ports on the first edge and electronic circ
7902915 Method and circuit for charging and discharging a circuit node March 8, 2011
A voltage circuit and method charges a circuit node to a first predetermined voltage. The first predetermined voltage charged onto the circuit node is used for a first predetermined function during a first time period. A portion of charge from the circuit node is removed to circuitry
7791367 Driver with selectable output impedance September 7, 2010
An integrated circuit is configured to be in a calibration mode of operation to establish a desired output impedance of a driver circuit. A predetermined constant voltage is established at a circuit node within the integrated circuit. A calibration current is conducted through a tran
7777330 High bandwidth cache-to-processing unit communication in a multiple processor/cache system August 17, 2010
A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache
7669100 System and method for testing and providing an integrated circuit having multiple modules or sub February 23, 2010
In an integrated circuit having a plurality of modules and/or submodules that each performs a substantially same function, defective modules and/or submodules are determined by creating a test signature from an input test pattern. The output of each module and/or submodule is compare
7492627 Memory with increased write margin bitcells February 17, 2009
A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a
7484140 Memory having variable refresh control and method therefor January 27, 2009
A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maint
7285976 Integrated circuit with programmable-impedance output buffer and method therefor October 23, 2007
An impedance matching between two integrated circuits is achieved using an impedance measuring circuit in the integrated circuit that contains an impedance-programmable output buffer (IPOB) that is to have its output impedance changed. The impedance measuring device is directly connected
7242626 Method and apparatus for low voltage write in a static random access memory July 10, 2007
An integrated circuit memory includes a plurality of memory cells, where each of the plurality of memory cells comprises a first storage node and a second storage node. Each of the plurality of memory cells comprises a transistor coupled between the first and second storage nodes and
7221613 Memory with serial input/output terminals for address and data and method therefor May 22, 2007
A memory (10) has a plurality of memory cells, a transceiver (56) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one o
7088632 Automatic hidden refresh in a dram and method therefor August 8, 2006
A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can oper
6781908 Memory having variable refresh control and method therefor August 24, 2004
A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maint
6765816 Storage circuit having single-ended write circuitry July 20, 2004
Single-ended write circuitry (18) in storage circuit (19) includes transistor (35) which provides aid in transitioning latch node (51) from a logic state "1" to a logic state "0" when latch node (50) is being transitioned from a logic state "0" to a logic state "1". Similarly, single
6760268 Method and apparatus for establishing a reference voltage in a memory July 6, 2004
A memory (110) uses memory cells not intended for user programming referred to as `dummy` cells (202, 206). When selected, the dummy cells provide a current that establishes a reference voltage substantially equal to one-half of voltage created in a bit line by a cell programmed to a one
6608789 Hysteresis reduced sense amplifier and method of operation August 19, 2003
A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two
6323704 Multiple voltage compatible I/O buffer November 27, 2001
Input and output buffer circuitry (12, 14, 16) is provided which are compatible with busses operating at different voltage levels. The buffer circuitry is self-configuring based on the type of bus to which it is coupled. The buffer circuitry includes voltage level detect circuitry (20)










 
 
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