| Patent Number |
Title Of Patent |
Date Issued |
| 7557048 |
Methods of forming semiconductor constructions |
July 7, 2009 |
| The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor |
| 7544554 |
Methods of forming gatelines and transistor devices |
June 9, 2009 |
| The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segmen |
| 7544533 |
Method and apparatus for providing an integrated circuit having p and n doped gates |
June 9, 2009 |
| A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and nitrogen concentrations and gate electrodes with differing conductivity types and active dopant concentrations. |
| 7470590 |
Methods of forming semiconductor constructions |
December 30, 2008 |
| The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication |
| 7462534 |
Methods of forming memory circuitry |
December 9, 2008 |
| The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The |
| 7456928 |
Systems and methods for controlling ambient pressure during processing of microfeature workpiece |
November 25, 2008 |
| Systems and methods for controlling ambient pressure during processing of microfeature workpieces, including during immersion lithography, are disclosed. A system in accordance with one embodiment includes a support configured to carry a microfeature workpiece with a surface of the m |
| 7442977 |
Gated field effect devices |
October 28, 2008 |
| This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between |
| 7439138 |
Method of forming integrated circuitry |
October 21, 2008 |
| The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, cond |
| 7419865 |
Methods of forming memory circuitry |
September 2, 2008 |
| The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging |
| 7411255 |
Dopant barrier for doped glass in memory devices |
August 12, 2008 |
| A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface |
| 7384849 |
Methods of forming recessed access devices associated with semiconductor constructions |
June 10, 2008 |
| The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access de |
| 7378704 |
Semiconductor constructions, and methods of forming semiconductor constructions |
May 27, 2008 |
| The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown ove |
| 7358568 |
Low resistance semiconductor process and structures |
April 15, 2008 |
| A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along e |
| 7315074 |
Use of DAR coating to modulate the efficiency of laser fuse blows |
January 1, 2008 |
| The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. |
| 7276433 |
Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of for |
October 2, 2007 |
| The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, cond |
| 7268384 |
Semiconductor substrate having first and second pairs of word lines |
September 11, 2007 |
| The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging |
| 7205600 |
Capacitor constructions with a barrier layer to threshold voltage shift inducing material |
April 17, 2007 |
| A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric layer formed at least wi |
| 7189662 |
Methods of forming semiconductor constructions |
March 13, 2007 |
| The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor |
| 7161857 |
Memory redundancy programming |
January 9, 2007 |
| A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device incl |
| 7161203 |
Gated field effect device comprising gate dielectric having different K regions |
January 9, 2007 |
| This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between |
| 7157757 |
Semiconductor constructions |
January 2, 2007 |
| The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segmen |
| 7151291 |
Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming cap |
December 19, 2006 |
| The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) |
| 7132371 |
Dopant barrier for doped glass in memory devices |
November 7, 2006 |
| A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface |
| 7119397 |
Double blanket ion implant method and structure |
October 10, 2006 |
| A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a re |
| 7115512 |
Methods of forming semiconductor constructions |
October 3, 2006 |
| The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication |
| 7112479 |
Methods of forming gatelines and transistor devices |
September 26, 2006 |
| The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segmen |
| 7008843 |
Methods of forming memory circuitry |
March 7, 2006 |
| The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging |
| 7006392 |
Memory redundancy programming |
February 28, 2006 |
| A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device incl |
| 6977418 |
Low resistance semiconductor process and structures |
December 20, 2005 |
| A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along e |
| 6967146 |
Isolation region forming methods |
November 22, 2005 |
| In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of |
| 6921692 |
Methods of forming memory circuitry |
July 26, 2005 |
| The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging |
| 6900515 |
Use of DAR coating to modulate the efficiency of laser fuse blows |
May 31, 2005 |
| The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. |
| 6894332 |
Apparatus for reducing electrical shorts from the bit line to the cell plate |
May 17, 2005 |
| A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate. |
| 6864138 |
Methods of forming capacitor structures and DRAM arrays |
March 8, 2005 |
| The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) |
| 6833575 |
Dopant barrier for doped glass in memory devices |
December 21, 2004 |
| A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface |
| 6825095 |
Methods of forming capacitors |
November 30, 2004 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6808982 |
Method of reducing electrical shorts from the bit line to the cell plate |
October 26, 2004 |
| A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate. |
| 6753617 |
Method for improving a stepper signal in a planarized surface over alignment topography |
June 22, 2004 |
| A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises |
| 6727139 |
Methods of electrically contacting to conductive plugs, methods of forming contact openings, and |
April 27, 2004 |
| Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafe |
| 6710420 |
Semiconductor construction of a trench |
March 23, 2004 |
| In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of |
| 6710390 |
Capacitors and DRAM arrays |
March 23, 2004 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6693014 |
Method of improving static refresh |
February 17, 2004 |
| A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a regio |
| 6617635 |
Integrated circuit devices having contact and container structures |
September 9, 2003 |
| Integrated circuitry fabricated using methods for forming contact structures and container structures, as described herein, are provided. The integrated circuitry formed by the methods of the present invention, for example DRAM structures, provide capacitors in containers having suff |
| 6605532 |
Structure for an electrical contact to a thin film in a semiconductor structure and method for m |
August 12, 2003 |
| A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making t |
| 6599840 |
Material removal method for forming a structure |
July 29, 2003 |
| Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. |
| 6596648 |
Material removal method for forming a structure |
July 22, 2003 |
| Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. |
| 6596642 |
Material removal method for forming a structure |
July 22, 2003 |
| Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. |
| 6593206 |
Isolation region forming methods |
July 15, 2003 |
| In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of |
| 6593183 |
Semiconductor processing method using a barrier layer |
July 15, 2003 |
| A semiconductor processing method includes forming a conductively doped plug of semiconductive material within a first insulative layer. A barrier layer to out diffusion of dopant material from the semiconductive material is formed over the doped plug. Examples include undoped oxide, suc |
| 6580114 |
Processing methods of forming a capacitor, and capacitor construction |
June 17, 2003 |
| Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node |
