| Patent Number |
Title Of Patent |
Date Issued |
| 7566628 |
Process for making a resistive memory cell with separately patterned electrodes |
July 28, 2009 |
| Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, |
| 7468525 |
Test structures for development of metal-insulator-metal (MIM) devices |
December 23, 2008 |
| In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and s |
| 7465956 |
Stacked organic memory devices and methods of operating and fabricating |
December 16, 2008 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 7384800 |
Method of fabricating metal-insulator-metal (MIM) device with stable data retention |
June 10, 2008 |
| In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of .alpha.-Ta is provided. The Ta of the first electrode is oxidized to form a Ta.sub.2O.sub.5 layer on the first electrode. A second electrode of .beta.-Ta is provided on the Ta.sub.2O.sub.5 layer. Such |
| 7232765 |
Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias |
June 19, 2007 |
| Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non |
| 6979837 |
Stacked organic memory devices and methods of operating and fabricating |
December 27, 2005 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 6977389 |
Planar polymer memory device |
December 20, 2005 |
| The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and |
| 6943096 |
Semiconductor component and method of manufacture |
September 13, 2005 |
| A semiconductor component having a metallization system that includes a multi-metal seed layer and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a lower level interconnect. A hardmask is formed over the dielectric layer and an o |
| 6870183 |
Stacked organic memory devices and methods of operating and fabricating |
March 22, 2005 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 6869878 |
Method of forming a selective barrier layer using a sacrificial layer |
March 22, 2005 |
| The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective |
| 6852586 |
Self assembly of conducting polymer for formation of polymer memory cell |
February 8, 2005 |
| The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that |
| 6836017 |
Protection of low-k ILD during damascene processing with thin liner |
December 28, 2004 |
| Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositin |
| 6791081 |
Method for determining pore characteristics in porous materials |
September 14, 2004 |
| A method for measuring porosity of nanoporous materials is provided using atomic force microscopy (AFM). A surface topology map with sub-atomic resolution is created using AFM wherein the pore shape and size can be determined by measuring the pores that intersect the top or fracture |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6784095 |
Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing |
August 31, 2004 |
| Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to |
| 6770905 |
Implantation for the formation of CuX layer in an organic memory device |
August 3, 2004 |
| An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semic |
| 6756672 |
Use of sic for preventing copper contamination of low-k dielectric layers |
June 29, 2004 |
| A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer |
| 6753247 |
Method(s) facilitating formation of memory cell(s) and patterned conductive |
June 22, 2004 |
| A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is appl |
| 6746971 |
Method of forming copper sulfide for memory cell |
June 8, 2004 |
| An organic memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The controllably conductive media changes its impedance when an ext |
| 6723635 |
Protection low-k ILD during damascene processing with thin liner |
April 20, 2004 |
| Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositin |
| 6713382 |
Vapor treatment for repairing damage of low-k dielectric |
March 30, 2004 |
| A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier |
| 6710452 |
Coherent diffusion barriers for integrated circuit interconnects |
March 23, 2004 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a bar |
| 6660619 |
Dual damascene metal interconnect structure with dielectric studs |
December 9, 2003 |
| A method for forming a dual damascene conductive line and conductive plug using porous low k dielectric materials in the via and trench layers. The via layer is provided with dense low k dielectric plugs that increase the mechanical strength of the porous low k dielectric layer that form |
| 6656763 |
Spin on polymers for organic memory devices |
December 2, 2003 |
| A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin- |
| 6599839 |
Plasma etch process for nonhomogenous film |
July 29, 2003 |
| A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an et |
| 6566283 |
Silane treatment of low dielectric constant materials in semiconductor device manufacturing |
May 20, 2003 |
| Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to |
| 6555461 |
Method of forming low resistance barrier on low k interconnect |
April 29, 2003 |
| A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. |
| 6518646 |
Semiconductor device with variable composition low-k inter-layer dielectric and method of making |
February 11, 2003 |
| Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectr |
| 6509267 |
Method of forming low resistance barrier on low k interconnect with electrolessly plated copper |
January 21, 2003 |
| A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. |
| 6475929 |
Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer produ |
November 5, 2002 |
| A method of manufacturing a low-k semiconductor structure including the steps of forming a low-k dielectric layer, forming a sacrificial etch stop layer adjacent the low-k dielectric layer, and applying energy to the sacrificial etch stop layer to diffuse a component of the sacrificial e |
| 6472336 |
Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material |
October 29, 2002 |
| Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. |
| 6468894 |
Metal interconnection structure with dummy vias |
October 22, 2002 |
| A metal interconnect structure and method of making the same provides a low k dielectric layer on a substrate that contains the first metal line. A plurality of vias are formed in the low k dielectric layer, along with a second metal line. A first set of the plurality of vias are connect |
| 6462417 |
Coherent alloy diffusion barrier for integrated circuit interconnects |
October 8, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an al |
| 6383950 |
Insulating and capping structure with preservation of the low dielectric constant of the insulat |
May 7, 2002 |
| An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and havin |
| 6380067 |
Method for creating partially UV transparent anti-reflective coating for semiconductors |
April 30, 2002 |
| The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then |
| 6361837 |
Method and system for modifying and densifying a porous film |
March 26, 2002 |
| The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed |
| 6352930 |
Bilayer anti-reflective coating and etch hard mask |
March 5, 2002 |
| In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically tran |
| 6326692 |
Insulating and capping structure with preservation of the low dielectric constant of the insulat |
December 4, 2001 |
| An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and havin |
| 6294460 |
Semiconductor manufacturing method using a high extinction coefficient dielectric photomask |
September 25, 2001 |
| A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a |
| 6291296 |
Method for removing anti-reflective coating layer using plasma etch process before contact CMP |
September 18, 2001 |
| The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane ( |
| 6232002 |
Bilayer anti-reflective coating and etch hard mask |
May 15, 2001 |
| In the manufacture of sub 0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically tran |
| 6221794 |
Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
April 24, 2001 |
| In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases |
| 6191030 |
Anti-reflective coating layer for semiconductor device |
February 20, 2001 |
| In a photo-lithographic step for providing contact points to lower layers of a semiconductor device, an anti-reflective coating (ARC) layer, such as FLARE 2.0.TM., is used to provide a good contact points to an underlayer. After the contact points are made, the anti-reflective coating la |
| 6174743 |
Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
January 16, 2001 |
| In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases |
| 6171947 |
Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
January 9, 2001 |
| In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition. |
| 6143672 |
Method of reducing metal voidings in 0.25 .mu.m AL interconnect |
November 7, 2000 |
| In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an alumin |
| 6136649 |
Method for removing anti-reflective coating layer using plasma etch process after contact CMP |
October 24, 2000 |
| The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (C |
| 5986344 |
Anti-reflective coating layer for semiconductor device |
November 16, 1999 |
| In a photo-lithographic step for providing contact points to lower layers of a semiconductor device, an anti-reflective coating (ARC) layer, such as FLARE 2.0.TM., is used to provide a good contact points to an underlayer. After the contact points are made, the anti-reflective coating la |
