| Patent Number |
Title Of Patent |
Date Issued |
| 7598749 |
Integrated circuit with fuse programming damage detection |
October 6, 2009 |
| An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in e |
| 7567449 |
One-time-programmable logic bit with multiple logic elements |
July 28, 2009 |
| A memory cell with a logic bit has a first one-time-programmable ("OTP") memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the sec |
| 7501879 |
eFuse resistance sensing scheme with improved accuracy |
March 10, 2009 |
| An eFuse sensing circuit replaces the inverters used to provide the "read" output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The r |
| 7312625 |
Test circuit and method of use thereof for the manufacture of integrated circuits |
December 25, 2007 |
| A test circuit for fabrication of transistors for Very Large Scale Integration ("VLSI") processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gat |
| 7301811 |
Cost efficient nonvolatile SRAM cell |
November 27, 2007 |
| A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in a first polysilicon |
| 7301194 |
Shrinkable and highly coupled double poly EEPROM with inverter |
November 27, 2007 |
| A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configur |
| 7294888 |
CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer |
November 13, 2007 |
| An electrically erasable programmable read-only memory ("CMOS NON-VOLATILE MEMORY") cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on t |
| 7280421 |
Non-volatile memory cell integrated with a latch |
October 9, 2007 |
| A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated c |
| 7092293 |
Non-volatile memory cell integrated with a latch |
August 15, 2006 |
| A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated c |
